Nonvolatile digital computing with ferroelectric FET

ABSTRACT

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&amp;R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 15/976,315, which is related to and claims the benefit ofpriority to U.S. Provisional Application Ser. No. 62/504,775 filed onMay 11, 2017, the entire contents of which is incorporated herein byreference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT

This invention was made with government support under Grant No.HR0011-13-3-0002 awarded by the Department of Defense/Defense AdvancedResearch Projects Agency (DARPA). The government has certain rights inthe invention.

FIELD OF THE INVENTION

Embodiments of the invention relate to nonvolatile a memory (NVM) devicethat can be configured for logic switching and/or digital computing. Forexample, embodiments of the NVM device can be configured as any one orcombination of a memory cell, a D flip flop (DFF), a Backup and Restorecircuit (B&R circuit), and/or a latch for a DFF.

BACKGROUND OF THE INVENTION

Conventional nonvolatile memories tend to require a large amount ofenergy for suitable operation. The energy consumed during backup andrestore operations can be factors that lead to this large energyrequirement. During backup and restore operations, high static current,long backup times to survive power supply variations, and/or longrestore times to cover supply recovery ramp can lead to a high totalenergy per backup and restore operation. Conventional nonvolatilememories can also be plagued with limited speed, limited endurance,and/or limited use of dynamic energy or power.

Not only can the effects of such limitations result in wasted energyconsumption, these and other limitations exhibited by conventionalnonvolatile memories may hinder implementation of energy savingtechniques. This inability to implement energy saving techniques can beexacerbated during frequent data access operations when the conventionalnonvolatile memory is used as a memory cell during computation and/orlogic switching.

Examples of conventional nonvolatile memories and logic switchingdevices can be appreciated from U.S. Patent Publication No.2001/0011743, U.S. Patent Publication No. 2004/0041186, U.S. PatentPublication No. 2009/0190430, U.S. Patent Publication No. 2011/0147807,U.S. Patent Publication No. 2012/0014169, and U.S. Patent PublicationNo. 2015/0089293.

SUMMARY OF THE INVENTION

Embodiments include nonvolatile a memory (NVM) device that can beconfigured for logic switching and/or digital computing. For example,embodiments of the NVM device can be configured as any one orcombination of a memory cell, a D flip flop (DFF), a Backup and Restorecircuit (B&R circuit), and/or a latch for a DFF.

Any of the NVM devices can have a Fe field effect transistors (FeFET)configured to exploit the I_(DS)−V_(G) hysteresis of the steep switch atlow voltage for logic memory synergy. The FeFET-based devices can beconfigured to include a wide hysteresis, a steep hysteresis edge, andhigh ratio between the two I_(DS) states at V_(G)=0. This can beachieved by shifting the hysteresis of the FeFET by Vth engineering andtuning other parameters by adjusting the ferroelectric layer thicknessand ferroelectric area. In some embodiments, the hysteresis can beshifted to center the hysteresis window around V_(G)=0, which mayprovide extra non-volatility to the FeFET-based device. Some embodimentscan be configured to operate on higher ON-state current and lowerOFF-state current to provide faster restore operations, as well asprovide immunity to device variations.

Embodiments of the FeFET-based devices can be used to producenonvolatile DFFs that maintain their state during power outages. TheseDFFs, used as nonvolatile memories, can facilitate computing without theloss of computation states during a power failure, which can be achievedby nonvolatile processing techniques of embedding the FeFET-based deviceon a memory chip so that the FeFET-based device can serve as a logictransistor. In some embodiments, the DFFs can be configured to operatewith external backup and restore control signals. In some embodiments,the DFFs can be configured to operate without external backup andrestore control signals, which can be achieved by the addition oftransistors to the nonvolatile memory cell design. Embodiments of theDFF can be configured to consume negligible static current in backup andin restore operations, be energy efficient, have low latency backup andrestore operations, and have low energy-delay overhead.

In at least one embodiment, a nonvolatile memory (NVM) device can bemade having a circuit topology with at least one Fe field effecttransistor (FeFET) configured to exhibit a wide current-voltage (I-V)hysteresis covering zero gate bias.

In at least one embodiment, the NVM device circuit topology can beconfigured as a backup and restore circuit (B&R circuit). The B&Rcircuit can include a first transistor, M₁, M₁ having an M₁-source, anM₁-gate, and an M₁-drain. The B&R circuit can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. TheB&R circuit can include a third transistor, M₃, M₃ having an M₃-source,an M₃-gate, and an M₃-drain. The B&R circuit can include a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain. TheB&R circuit can include a fifth transistor, M₅, M₅ having an M₅-source,an M₅-gate, and an M₅-drain. The B&R circuit can include a sixthtransistor, M₆, M₆ having an M₆-source, an M₆-gate, and an M₆-drain. TheB&R circuit can include a seventh transistor, M₇, M₇ having anM₇-source, an M₇-gate, and an M₇-drain. The B&R circuit can include aneighth transistor, M₈, M₈ having an M₈-source, an M₈-gate, and anM₈-drain. The B&R circuit can include a first branch and a secondbranch, the first branch including M₁, M₂, M₅, M₇, and a ground, GND,the second branch including M₃, M₄, M₆, and M₈. Each of M₁, M₂, M₃, M₄,M₇, and M₈ can be a metal-oxide-semiconductor field-effect transistor(MOSFET) and each of M₅ and M₆ can be a FeFET. M₁-gate can be connectedto a backup control signal input, B_(kp_input) and M₃-gate. M₁-drain canbe connected to M₂-drain. M₁-drain can be configured to be connected toa slave latch via the first branch. M₁-source can be connected toM₅-source and M₇-drain. M₂-drain can be connected to M₁-drain. M₂-draincan be configured to be connected to the slave latch via the firstbranch. M₂-gate can be connected to a backup and restore control signalinput, B_(kp)+R_(str) and M₃-gate. M₂-source can be connected toM₆-gate, M₅-drain, M₅-gate, M₆-drain, and M₃-source. M₃-drain can beconnected to M₄-drain. M₃-drain can be configured to be connected to theslave latch via the second branch. M₃-gate can be connected toB_(kp)+R_(str) and M₁-gate. M₃-source can be connected to M₅-gate,M₆-drain, M₅-drain, M₂-source, and M₆-gate. M₄-drain can be connected toM₃-drain. M₄-drain can be configured to be connected to the slave latchvia the second branch. M₄-gate can be connected to a backup controlsignal output, B_(kp_output). M₄-source can be connected to M₆-sourceand M₈-drain. M₅-drain can be connected to M₂-source, M₅-gate, M₆-gate,M₆-drain, and M₃-source. M₅-gate can be connected to M₃-source,M₆-drain, M₆-gate, M₂-source, and M₅-drain. M₅-source can be connectedto M₇-drain and M₁-source. M₆-drain can be connected to M₃-source,M₅-gate, M₆-gate, M₅-drain, and M₂-source. M₆-gate can be connected toM₂-source, M₅-drain, M₅-gate, M₆-drain, and M₃-source. M₆-source can beconnected to M₄-source and M₈-drain. M₇-drain can be connected toM₁-source and M₅-source. M₇-gate can be connected to a restore inputcontrol signal, R_(str). M₇-source can be connected to GND via the firstbranch. M₈-drain can be connected to M₄-source and M₆-source. M₈-gatecan be connected to M₇-gate. M₈-source can be connected to GND via thesecond branch.

In at least one embodiment, the NVM device the circuit topology can beconfigured as a D-Flip Flop (DFF). The DFF can include a master latch, aslave latch, and a backup and restore circuit (B&R circuit). The masterlatch can include a first master inverter M_(INV1), a second masterinverter, M_(INV2), a third master inverter, M_(INV3), and a mastertransmission gate, M_(GATE). Input of M_(INV1) can be connected to adata input signal, D. Output of M_(INV1) can be connected to input ofM_(INV2). Input of M_(INV2) can be connected to output of M_(INV1).Output of M_(INV2) can be connected to input of M_(INV3). Input ofM_(INV3) can be connected to output of M_(INV2). Output of M_(INV3) canbe connected to input of M_(GATE). Input of M_(GATE) can be connected tooutput of M_(INV3). Output of M_(GATE) can be connected to input ofM_(INV2) and output of M_(INV1). The slave latch can include a firstslave inverter, S_(INV1), a second slave inverter, S_(INV2), a thirdslave inverter, S_(INV3), and a slave transmission gate, S_(GATE). Inputof S_(INV1) can be connected to output of M_(INV2). Input of S_(INV2)can be connected to output of S_(INV1). Output of S_(INV2) can beconnected to input of S_(INV3) and to a data output Q. Input of S_(INV3)can be connected to output of S_(INV2). Output of S_(INV3) can beconnected to input of S_(GATE). Output of S_(GATE) can be connected toinput of S_(INV2) and output of S_(INV1). The B&R circuit can include afirst transistor, M₁, M₁ having an M₁-source, an M₁-gate, and anM₁-drain. The B&R circuit can include second transistor, M₂, M₂ havingan M₂-source, an M₂-gate, and an M₂-drain. The B&R circuit can include athird transistor, M₃, M₃ having an M₃-source, an M₃-gate, and anM₃-drain. The B&R circuit can include a fourth transistor, M₄, M₄ havingan M₄-source, an M₄-gate, and an M₄-drain. The B&R circuit can include afifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, and anM₅-drain. The B&R circuit can include a sixth transistor, M₆, M₆ havingan M₆-source, an M₆-gate, and an M₆-drain. The B&R circuit can include aseventh transistor, M₇, M₇ having an M₇-source, an M₇-gate, and anM₇-drain. The B&R circuit can include an eighth transistor, M₈, M₈having an M₈-source, an M₈-gate, and an M₈-drain. The B&R circuit caninclude a first branch and a second branch, the first branch includingM₁, M₂, M₅, M₇, and a ground, GND, the second branch including M₃, M₄,M₆, and M₈. Each of M₁, M₂, M₃, M₄, M₇, and M₈ can be ametal-oxide-semiconductor field-effect transistor (MOSFET) and each ofM₅ and M₆ can be FeFET. M₁-gate can be connected to a backup controlsignal input, B_(kp_input) and M₃-gate. M₁-drain can be connected toM₂-drain. M₁-drain can be configured to be connected to the slave latchvia the first branch. M₁-source can be connected to M₅-source andM₇-drain. M₂-drain can be connected to M₁-drain. M₂-drain can beconfigured to be connected to the slave latch via the first branch.M₂-gate can be connected to a backup and restore control signal input,B_(kp)+R_(str) and M₃-gate. M₂-source can be connected to M₆-gate,M₅-drain, M₅-gate, M₆-drain, and M₃-source. M₃-drain can be connected toM₄-drain. M₃-drain can be configured to be connected to the slave latchvia the second branch. M₃-gate can be connected to B_(kp)+R_(str) andM₁-gate. M₃-source can be connected to M₅-gate, M₆-drain, M₅-drain,M₂-source, and M₆-gate. M₄-drain can be connected to M₃-drain. M₄-draincan be configured to be connected to the slave latch via the secondbranch. M₄-gate can be connected to a backup control signal output,B_(kp_output). M₄-source can be connected to M₆-source and M₈-drain.M₅-drain can be connected to M₂-source, M₅-gate, M₆-gate, M₆-drain, andM₃-source. M₅-gate can be connected to M₃-source, M₆-drain, M₆-gate,M₂-source, and M₅-drain. M₅-source can be connected to M₇-drain andM₁-source. M₆-drain can be connected to M₃-source, M₅-gate, M₆-gate,M₅-drain, and M₂-source. M₆-gate can be connected to M₂-source,M₅-drain, M₅-gate, M₆-drain, and M₃-source. M₆-source can be connectedto M₄-source and M₈-drain. M₇-drain can be connected to M₁-source andM₅-source. M₇-gate can be connected to a restore input control signal,R_(str). M₇-source can be connected to GND via the first branch.M₈-drain can be connected to M₄-source and M₆-source. M₈-gate can beconnected to M₇-gate. M₈-source can be connected to GND via the secondbranch.

In at least one embodiment the NVM device the circuit topology can beconfigured as a latch configured to have a differential-driving inputpair D/DN. The latch can include a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain. The latch can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. Thelatch can include a third transistor, M₃, M₃ having an M₃-source, anM₃-gate, and an M₃-drain. The latch can include a fourth transistor, M₄,M₄ having an M₄-source, an M₄-gate, and an M₄-drain. The latch caninclude a fifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, andan M₅-drain. The latch can include a sixth transistor, M₆, M₆ having anM₆-source, an M₆-gate, and an M₆-drain. The latch can include a seventhtransistor, M₇, M₇ having an M₇-source, an M₇-gate, and an M₇-drain. Thelatch can include an eighth transistor, M₈, M₈ having an M₈-source, anM₈-gate, and an M₈-drain. Each of M₁, M₂, M₃, M₄, M₇, and M₈ can be ametal oxide semiconductor field effect transistor (MOSFET). Each of M₅and M₆ can be a FeFET. M₁-drain can be connected to M₃-gate, M₃-source,M₄-source, M₄-gate, a data output Q, M₂-drain, M₅-gate, M₇-gate,M₅-drain, a data output QN, M₆-drain, M₆-gate, and M₈-gate. M₁-gate canbe connected to a clock driver CLK. M₁-source can be connected to a datainput D. M₂-drain can be connected to M₃-gate, M₃-source, M₄-source,M₄-gate, data output Q, M₁-drain, M₅-gate, M₇-gate, M₅-drain, dataoutput QN, M₆-drain, M₆-gate, and M₈-gate. M₂-gate can be connected toM₁-gate. M₂-source can be connected to a data input DN. M₃-drain can beconnected to a voltage supply V_(DD). M₃-gate can be connected toM₃-source, M₄-source, M₄-gate, data output Q, M₁-drain, M₂-drain,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. M₃-source can be connected to M₃-gate, M₄-source, M₄-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data outputQN, M₆-drain, M₆-gate, and M₈-gate. M₄-drain can be connected to V_(DD).M₄-gate can be connected to M₃-source, M₄-source, M₃-gate, data outputQ, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN,M₆-drain, M₆-gate, and M₈-gate. M₄-source can be connected to M₃-source,M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate,M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate. M₅-drain beconnected to M₄-source, M₃-source, M₄-gate, M₃-gate, data output Q,M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN,M₆-drain, M₆-gate, and M₈-gate. M₅-gate can be connected to M₄-source,M₃-source, M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain,M₅-drain, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. M₅-source can be connected to M₇-drain. M₆-drain can beconnected to M₄-source, M₃-source, M₄-gate, M₃-gate, data output Q,M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN,M₅-drain, M₆-gate, and M₈-gate. M₆-gate can be connected to M₄-source,M₃-source, M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate,M₇-gate, M₅-drain, data output QN, M₅-drain, M₆-drain, and M₈-gate.M₆-source can be connected to M₈-drain. M₇-drain can be connected toM₅-source. M₇-gate can be connected to M₆-gate, M₄-source, M₃-source,M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate, M₅-drain,data output QN, M₅-drain, M₆-drain, and M₈-gate. M₇-source can beconnected to ground, GND. M₈-drain can be connected to M₆-source.M₈-gate can be connected to M₇-gate, M₆-gate, M₄-source, M₃-source,M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate, M₅-drain,data output QN, M₅-drain, and M₆-drain. M₈-source can be connected toGND.

In at least one embodiment, the NVM device circuit topology can beconfigured as a latch configured to have an input D. The latch caninclude a first transistor, M₁, M₁ having an M₁-source, an M₁-gate, andan M₁-drain. The latch can include a second transistor, M₂, M₂ having anM₂-source, an M₂-gate, and an M₂-drain. The latch can include a thirdtransistor, M₃, M₃ having an M₃-source, an M₃-gate, and an M₃-drain. Thelatch can include a fourth transistor, M₄, M₄ having an M₄-source, anM₄-gate, and an M₄-drain. The latch can include a fifth transistor, M₅,M₅ having an M₅-source, an M₅-gate, and an M₅-drain. The latch caninclude a sixth transistor, M₆, M₆ having an M₆-source, an M₆-gate, andan M₆-drain. The latch can include a seventh transistor, M₇, M₇ havingan M₇-source, an M₇-gate, and an M₇-drain. The latch can include aneighth transistor, M₈, M₈ having an M₈-source, an M₈-gate, and anM₈-drain. The latch can include a ninth transistor, M₉, M₉ having anM₉-source, an M₉-gate, and an M₉-drain. The latch can include a tenthtransistor, M₁₀, M₁₀ having an M₁₀-source, an M₁₀-gate, and anM₁₀-drain. The latch can include an eleventh transistor, M₁₁, M₁₁ havingan M₁₁-source, an M₁₁-gate, and an M₁₂-drain. The latch can include atwelfth transistor, M₁₂, M₁₂ having an M₁₂-source, an M₁₂-gate, and anM₁₂-drain. The latch can include a thirteenth transistor, M_(5b), M_(5b)having an M_(5b)-source, an M_(5b)-gate, and an M_(5b)-drain. The latchcan include a fourteenth transistor, M_(6b), M_(6b) having anM_(th)-source, an M_(6b)-gate, and an M_(6b)-drain. Each of M₁, M₂, M₃,M₄, M₇, M₈, M₉, M₁₀, and M₁₁ can be a metal oxide semiconductor fieldeffect transistor (MOSFET). Each of M₅ and M₆ can be a FeFET. M₁-draincan be connected to M₂-drain and a data input D. M₁-gate can beconnected to a clock driver, CLK. M₁-source can be connected toM₂-source, M₃-gate, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source,M₉-source, M₁₀-source, M₅-drain, and M_(5b)-drain. M₂-drain can beconnected to M₁-drain and data input D. M₂-gate can be connected to CLK.M₂-source can be connected to M₁-source, M₃-gate, M₅-gate, M₇-gate,M₁₁-source, M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain. M₃-drain can be connected to a V_(DD). M₃-gate can beconnected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain. M₃-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-gate, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain. M₄-drain can be connected to avoltage supply, V_(DD). M₄-gate can be connected to a data output QN, adata output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain,M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₄-source can beconnected to data output QN, data output Q, M₆-gate, M₈-gate, M₄-gate,M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain.M₅-drain can be connected to M₁-source, M₂-source, M₅-gate, M₇-gate,M₁₁-source, M₁₂-source, M₃-source, M₉-source, M₁₀-source, andM_(5b)-drain. M₅-gate can be connected to M₁-source, M₂-source,M₅-drain, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M_(5b)-gate, and M_(5b)-drain. M₅-source can be connected toM₇-drain. M_(5b)-drain can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, and M₅-drain. M_(5b)-gate can be connected to M₅-gate.M_(5b)-source can be connected to ground, GND. M₆-drain can be connectedto data output QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₄-gate. M₆-gate canbe connected to data output QN, data output Q, M₆-drain, M_(6b)-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₄-gate. M₆-source can be connected to M₈-drain.M_(6b)-drain can be connected to data output QN, data output Q, M₆-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain, M₄-gate,and M₆-drain. M_(6b)-gate can be connected to M₆-gate. M_(6b)-source canbe connected to GND. M₇-drain can be connected to M₅-source. M₇-gate canbe connected to M₁-source, M₂-source, M₅-gate, M₅-drain, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M_(5b)-drain.M₇-source can be connected to GND. M₈-drain can be connected toM₆-source. M₈-gate can be connected to data output QN, data output Q,M₆-gate, M₄-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₆-drain. M₈-source can be connected to GND. M₉-draincan be connected to data output QN, data output Q, M₆-gate, M₈-gate,M₄-source, M₄-gate, M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, andM₆-drain. M₉-gate can be connected to V_(DD). M₉-source can be connectedto M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source,M₃-source, M₅-drain, M₁₀-source, and M_(5b)-drain. M₁₀-drain can beconnected to data output QN, data output Q, M₆-gate, M₈-gate, M₄-source,M₉-drain, M₄-gate, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain.M₁₀-gate can be connected to GND. M₁₀-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source,M₃-source, M₉-source, M₅-drain, and M_(5b)-drain. M₁₁-drain can beconnected to data output QN, data output Q, M₆-gate, M₈-gate, M₄-source,M₉-drain, M₁₀-drain, M₄-gate, M₁₂-drain, M_(6b)-drain, and M₆-drain.M₁₁-gate can be connected to CLK. M₁₁-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₅-drain, M₁₂-source, M₃-source,M₉-source, M₁₀-source, and M_(5b)-drain. M₁₂-drain can be connected todata output QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₄-gate, M_(6b)-drain, and M₆-drain. M₁₂-gate canbe connected to CLK. M₁₂-source can be connected to M₁-source,M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₅-drain, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain.

In at least one embodiment the NVM device circuit topology can beconfigured as a latch configured to have a differential-driving inputpair D/DN. The latch can include a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain. The latch can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. Thelatch can include a third transistor, M₃, M₃ having an M₃-source, anM₃-gate, and an M₃-drain. The latch can include a fourth transistor, M₄,M₄ having an M₄-source, an M₄-gate, and an M₄-drain. The latch caninclude a fifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, andan M₅-drain. The latch can include a sixth transistor, M₆, M₆ having anM₆-source, an M₆-gate, and an M₆-drain. The latch can include a seventhtransistor, M₇. M₇ having an M₇-source, an M₇-gate, and an M₇-drain. Thelatch can include an eighth transistor, M₈, M₈ having an M₈-source, anM₈-gate, and an M₈-drain. Each of M₁, M₂, M₃, M₄, M₇, and M₈ can be ametal oxide semiconductor field effect transistor (MOSFET). Each of M₅and M₆ can be a FeFET. M₁-drain can be connected to a data input D.M₁-gate can be connected to a clock driver, CLK. M₁-source can beconnected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain,a data output Q, a data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate. M₂-drain can be connected to data input DN.M₂-gate can be connected to M₁-gate. M₂-source can be connected toM₅-gate, M₃-gate, M₅-source, M₁-source, M₇-gate, M₇-drain, a data outputQ, a data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₃-drain can be connected to a V_(DD). M₃-gate can be connected toM₅-gate, M₁-source, M₅-source, M₂-source, M₇-gate, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₃-source can be connected to M₅-drain. M₄-drain can be connected toV_(DD). M₄-gate can be connected to M₅-gate, M₃-gate, M₅-source,M₂-source, M₇-gate, M₇-drain, data output Q, data output QN, M₆-source,M₈-drain, M₈-gate, M₆-gate, and M₁-source. M₄-source can be connected toM₆-drain. M₅-drain can be connected to M₃-source. M5-gate can beconnected to M₁-source, M₃-gate, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate. M₅-source can be connected to M₅-gate, M₃-gate,M₁-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate. M₆-drain can beconnected to M₄-source. M₆-gate can be connected to M₅-gate, M₃-gate,M₅-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₁-source, and M₄-gate. M₆-source can beconnected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain,data output Q, data output QN, M₁-source, M₈-drain, M₈-gate, M₆-gate,and M₄-gate. M₇-drain can be connected to M₅-gate, M₃-gate, M₅-source,M₂-source, M₇-gate, M₁-source, data output Q, data output QN, M₆-source,M₈-drain, M₈-gate, M₆-gate, and M₄-gate. M₇-gate can be connected toM₅-gate, M₃-gate, M₅-source, M₂-source, M₁-source, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₇-source can be connected to ground, GND. M₈-drain can be connected toM₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain, data outputQ, data output QN, M₆-source, M₁-source, M₈-gate, M₆-gate, and M₄-gate.M₈-gate can be connected to M₅-gate, M₃-gate, M₅-source, M₂-source,M₇-gate, M₇-drain, data output Q, data output QN, M₆-source, M₈-drain,M₁-source, M₆-gate, and M₄-gate. M₈-source can be connected to GND.

In at least one embodiment the NVM device circuit topology can beconfigured as a latch configured to have a differential-driving inputpair D/DN. The latch can include a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain. The latch can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. Thelatch can include a third transistor, M₃, M₃ having an M₃-source, anM₃-gate, and an M₃-drain. The latch can include a fourth transistor, M₄,M₄ having an M₄-source, an M₄-gate, and an M₄-drain. The latch caninclude a fifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, andan M₅-drain. The latch can include a sixth transistor, M₆, M₆ having anM₆-source, an M₆-gate, and an M₆-drain. The latch can include a seventhtransistor, M₇. M₇ having an M₇-source, an M₇-gate, and an M₇-drain. Thelatch can include an eighth transistor, M₈, M₈ having an M₈-source, anM₈-gate, and an M₈-drain. The latch can include a ninth transistor, M₉,M₉ having an M₉-source, an M₉-gate, and an M₉-drain. The latch caninclude a tenth transistor, M₁₀, M₁₀ having an M₁₀-source, an M₁₀-gate,and an M₁₀-drain. Each of M₁, M₂, M₃, M₄, M₉, and M₁₀ can be a metaloxide semiconductor field effect transistor (MOSFET). Each of M₅, M₆,M₇, and M₈ can be a FeFET. M₁-drain can be connected to a data input D.M₁-gate can be connected to a clock driver, CLK. M₁-source can beconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source,M₆-source, a data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, a dataoutput QN, M₈-gate, and M₁₀-gate. M₂-drain can be connected to a datainput DN. M₂-gate can be connected to M₁-gate. M₂-source can beconnected to M₅-gate, M₃-gate, M₁-source, M₇-gate, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁₀-gate. M₃-drain can be connected to a voltagesupply, V_(DD). M₃-gate can be connected to M₅-gate, M₁-source,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₃-source can be connected to M₅-drain. M₄-drain can beconnected to V_(DD). M₄-gate can be connected to M₅-gate, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₁-source, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₄-source can be connected to M₆-drain. M₅-drain can beconnected to M₃-source. M₅-gate c can be connected to M₁-source,M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data outputQ, M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₅-source can be connected to M₅-gate, M₃-gate, M₂-source,M₇-gate, M₉-gate, M₁-source, M₆-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₆-drain canbe connected to M₄-source. M₆-gate can be connected to M₅-gate, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₁-source, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₆-source can be connected to M₅-gate, M₃-gate, M₂-source,M₇-gate, M₉-gate, M₅-source, M₁-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₇-drain canbe connected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate, M₁-source,M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₇-gate can beconnected to M₅-gate, M₃-gate, M₂-source, M₁-source, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁₀-gate. M₇-source can be connected toM₉-drain. M₁₀-drain can be connected to M₈-source. M₁₀-gate can beconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁-source. M₁₀-source can be connected toground, GND.

In at least one embodiment the NVM device circuit topology can beconfigured as a D-Flip Flop (DFF). The DFF can include a master latch, aslave latch, and a backup and restore circuit (B&R circuit). The slavelatch can include a first transistor, M₁, M₁ having an M₁-source, anM₁-gate, and an M₁-drain. The slave latch can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. Theslave latch can include a third transistor, M₃, M₃ having an M₃-source,an M₃-gate, and an M₃-drain. The slave latch can include a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain. Theslave latch can include a fifth transistor, M₅, M₅ having an M₅-source,an M₅-gate, and an M₅-drain. The slave latch can include a sixthtransistor, M₆, M₆ having an M₆-source, an M₆-gate, and an M₆-drain. Theslave latch can include a seventh transistor, M₇, M₇ having anM₇-source, an M₇-gate, and an M₇-drain. The slave latch can include aneighth transistor, M₈, M₈ having an M₈-source, an M₈-gate, and anM₈-drain. Each of M₁, M₂, M₃, M₄, M₇, and M₈ can be a metal oxidesemiconductor field effect transistor (MOSFET). Each of M₅ and M₆ can bea FeFET. M₁-drain can be connected to M₃-gate, M₃-source, M₄-source,M₄-gate, a data output Q, M₂-drain, M₅-gate, M₇-gate, M₅-drain, a dataoutput QN, M₆-drain, M₆-gate, and M₈-gate. M₁-gate can be connected to aclock driver CLK. M₁-source can be connected to a data input D. M₂-draincan be connected to M₃-gate, M₃-source, M₄-source, M₄-gate, data outputQ, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. M₂-gate can be connected to M₁-gate. M₂-source can be connectedto a data input DN. M₃-drain can be connected to a voltage supplyV_(DD). M₃-gate can be connected to M₃-source, M₄-source, M₄-gate, dataoutput Q, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN,M₆-drain, M₆-gate, and M₈-gate. M₃-source can be connected to M₃-gate,M₄-source, M₄-gate, data output Q, M₂-drain, M₅-gate, M₇-gate, M₅-drain,data output QN, M₆-drain, M₆-gate, and M₈-gate. M₄-drain can beconnected to V_(DD). M₄-gate can be connected to M₃-source, M₄-source,M₃-gate, data output Q, M₂-drain, M₅-gate, M₇-gate, M₅-drain, dataoutput QN, M₆-drain, M₆-gate, and M₈-gate. M₄-source can be connected toM₃-source, M₄-gate, M₃-gate, data output Q, M₂-drain, M₅-gate, M₇-gate,M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate. M₅-drain beconnected to M₄-source, M₃-source, M₄-gate, M₃-gate, data output Q,M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate,and M₈-gate. M₅-gate can be connected to M₄-source, M₃-source, M₄-gate,M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-drain, M₇-gate, M₅-drain,data output QN, M₆-drain, M₆-gate, and M₈-gate. M₅-source can beconnected to M₇-drain. M₆-drain can be connected to M₄-source,M₃-source, M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate,M₇-gate, M₅-drain, data output QN, M₅-drain, M₆-gate, and M₈-gate.M₆-gate can be connected to M₄-source, M₃-source, M₄-gate, M₃-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data outputQN, M₅-drain, M₆-drain, and M₈-gate. M₆-source can be connected toM₈-drain. M₇-drain can be connected to M₅-source. M₇-gate can beconnected to M₆-gate, M₄-source, M₃-source, M₄-gate, M₃-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₅-drain, data output QN,M₅-drain, M₆-drain, and M₈-gate. M₇-source can be connected to ground,GND. M₈-drain can be connected to M₆-source. M₈-gate can be connected toM₇-gate, M₆-gate, M₄-source, M₃-source, M₄-gate, M₃-gate, data output Q,M₁-drain, M₂-drain, M₅-gate, M₅-drain, data output QN, M₅-drain, andM₆-drain. M₈-source can be connected to GND.

In at least one embodiment M₁ can be replaced with a first slavetransmission gate, S_(GATE1) and M₂ can be replaced with a second slavetransmission gate, S_(GATE2). Output of S_(GATE1) can be connected toM₃-gate, M₃-source, M₄-source, M₄-gate, data output Q, S_(GATE2) output,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. Output of S_(GATE2) can be connected to M₃-gate, M₃-source,M₄-source, M₄-gate, data output Q, S_(GATE1) output, M₅-gate, M₇-gate,M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate. The masterlatch can be connected to the slave latch via S_(GATE1) and S_(GATE2).

The master latch can have a first master transmission gate M_(GATE1), afirst master inverter, M_(INV1), a second master inverter, M_(INV2), anda second master transmission gate, M_(GATE2). Input of M_(GATE1) can beconnected to a data input signal, D. Output of M_(GATE1) can beconnected to input of M_(INV1) and input of S_(GATE1). Input of M_(INV1)can be connected to output of M_(GATE1). Output of M_(INV1) can beconnected to input of M_(INV2) and input of S_(GATE2). Input of M_(INV2)can be connected to output of M_(INV1). Output of M_(INV2) can beconnected to input of M_(GATE2). Input of M_(GATE2) can be connected tooutput of M_(INV2). Output of M_(GATE2) can be connected to input ofM_(GATE1) and output of M_(INV1).

M₁ can be replaced with a first slave inverter, S_(INV1) and M₂ can bereplaced with a second slave inverter, S_(INV2). Output of S_(INV1) canbe connected to M₃-gate, M₃-source, M₄-source, M₄-gate, data output Q,S_(INV2) output, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain,M₆-gate, and M₈-gate. Output of S_(INV2) can be connected to M₃-gate,M₃-source, M₄-source, M₄-gate, data output Q, S_(INV1) output, M₅-gate,M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate.

The master latch can be connected to the slave latch via S_(INV1) andS_(INV2). The master latch can have a first master transmission gateM_(GATE1), a first master inverter, M_(INV1), a second master inverter,M_(INV2), and a second master transmission gate, M_(GATE2). Input ofM_(GATE1) can be connected to a data input signal, D. Output ofM_(GATE1) can be connected to input of M_(INV1) and input of S_(INV1).Input of M_(INV1) can be connected to output of M_(GATE1). Output ofM_(INV1) can be connected to input of M_(INV2) and input of S_(INV2).Input of M_(INV2) can be connected to output of M_(INV1). Output ofM_(INV2) can be connected to input of M_(GATE2). Input of M_(GATE2) canbe connected to output of M_(INV2). Output of M_(GATE2) can be connectedto input of M_(GATE1) and output of M_(INV1).

In at least one embodiment the NVM device circuit topology can beconfigured as a D-Flip Flop (DFF). The DFF can include a master latch, aslave latch, and a backup and restore circuit (B&R circuit). The slavelatch can include a first transistor, M₁, M₁ having an M₁-source, anM₁-gate, and an M₁-drain. The slave latch can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. Theslave latch can include a third transistor, M₃, M₃ having an M₃-source,an M₃-gate, and an M₃-drain. The slave latch can include a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain. Theslave latch can include a fifth transistor, M₅, M₅ having an M₅-source,an M₅-gate, and an M₅-drain. The slave latch can include a sixthtransistor, M₆, M₆ having an M₆-source, an M₆-gate, and an M₆-drain. Theslave latch can include a seventh transistor, M₇, M₇ having anM₇-source, an M₇-gate, and an M₇-drain. The slave latch can include aneighth transistor, M₈, M₈ having an M₈-source, an M₈-gate, and anM₈-drain. The slave latch can include a ninth transistor, M₉, M₉ havingan M₉-source, an M₉-gate, and an M₉-drain. The slave latch can include atenth transistor, M₁₀, M₁₀ having an M₁₀-source, an M₁₀-gate, and anM₁₀-drain. The slave latch can include an eleventh transistor, M₁₁, M₁₁having an M₁₁-source, an M₁₁-gate, and an M₁₁-drain. The slave latch caninclude a twelfth transistor, M₁₂, M₁₂ having an M₁₂-source, anM₁₂-gate, and an M₁₂-drain. The slave latch can include a thirteenthtransistor, M_(5b), M_(5b) having an M_(5b)-source, an M_(5b)-gate, andan M_(5b)-drain. The slave latch can include a fourteenth transistor,M_(6b) M_(6b) having an M_(6b)-, source, an M_(6b)-gate, and anM_(6b)-drain. Each of M₁, M₂, M₃, M₄, M₇, M₈, M₉, M₁₀, and M₁₁ can be ametal oxide semiconductor field effect transistor (MOSFET). Each of M₅and M₆ can be a FeFET. M₁-drain can be connected to M₂-drain and a datainput D. M₁-gate can be connected to a clock driver, CLK. M₁-source canbe connected to M₂-source, M₃-gate, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain. M₂-drain can be connected to M₁-drain and data input D.M₂-gate can be connected to CLK. M₂-source can be connected toM₁-source, M₃-gate, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source,M₉-source, M₁₀-source, M₅-drain, and M_(5b)-drain. M₃-drain can beconnected to a V_(DD). M₃-gate can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain. M₃-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-gate,M₉-source, M₁₀-source, M₅-drain, and M_(5b)-drain. M₄-drain can beconnected to a voltage supply, V_(DD). M₄-gate can be connected to adata output QN, a data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₄-sourcecan be connected to data output QN, data output Q, M₆-gate, M₈-gate,M₄-gate, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, andM₆-drain. M₅-drain can be connected to M₁-source, M₂-source, M₅-gate,M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source, M₁₀-source, andM_(5b)-drain. M₅-gate can be connected to M₁-source, M₂-source,M₅-drain, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M_(5b)-gate, and M_(5b)-drain. M₅-source can be connected toM₇-drain. M_(5b)-drain can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, and M₅-drain. M_(5b)-gate can be connected to M₅-gate.M_(5b)-source can be connected to ground, GND. M₆-drain can be connectedto data output QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₄-gate. M₆-gate canbe connected to data output QN, data output Q, M₆-drain, M_(6b)-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₄-gate. M₆-source can be connected to M₈-drain.M_(6b)-drain can be connected to data output QN, data output Q, M₆-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain, M₄-gate,and M₆-drain. M_(6b)-gate can be connected to M₆-gate. M_(th)-source canbe connected to GND. M₇-drain can be connected to M₅-source. M₇-gate canbe connected to M₁-source, M₂-source, M₅-gate, M₅-drain, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M_(5b)-drain.M₇-source can be connected to GND. M₈-drain can be connected toM₆-source. M₈-gate can be connected to data output QN, data output Q,M₆-gate, M₄-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₆-drain. M₈-source can be connected to GND. M₉-draincan be connected to data output QN, data output Q, M₆-gate, M₈-gate,M₄-source, M₄-gate, M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, andM₆-drain. M₉-gate can be connected to V_(DD). M₉-source can be connectedto M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source,M₃-source, M₅-drain, M₁₀-source, and M_(5b)-drain. M₁₀-drain can beconnected to data output QN, data output Q, M₆-gate, M₈-gate, M₄-source,M₉-drain, M₄-gate, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain.M₁₀-gate can be connected to GND. M₁₀-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source,M₃-source, M₉-source, M₅-drain, and M_(5b)-drain. M₁₁-drain can beconnected to data output QN, data output Q, M₆-gate, M₈-gate, M₄-source,M₉-drain, M₁₀-drain, M₄-gate, M₁₂-drain, M_(6b)-drain, and M₆-drain.M₁₁-gate can be connected to CLK. M₁₁-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₅-drain, M₁₂-source, M₃-source,M₉-source, M₁₀-source, and M_(5b)-drain. M₁₂-drain can be connected todata output QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₄-gate, M_(6b)-drain, and M₆-drain. M₁₂-gate canbe connected to CLK. M₁₂-source can be connected to M₁-source,M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₅-drain, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain.

Each of M₁ and M₂ can be replaced with a slave inverter, S_(INV). Outputof S_(INV) can be connected to M₃-gate, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain.

The master latch can be connected to the slave latch via S_(INV). Themaster latch can have a first master inverter M_(INV1), a second masterinverter, M_(INV2), a third master inverter, M_(INV3), and a mastertransmission gate, M_(GATE). Input of M_(INV1) can be connected to adata input signal, D. Output of M_(INV1) can be connected to input ofM_(INV2). Input of M_(INV2) can be connected to output of M_(INV1).Output of M_(INV2) can be connected to input of M_(INV3) and input ofS_(INV). Input of M_(INV3) can be connected to output of M_(INV2).Output of M_(INV3) can be connected to input of M_(GATE). Input ofM_(GATE) can be connected to output of M_(INV3). Output of M_(GATE) canbe connected to input of M_(INV2) and output of M_(INV1).

In at least one embodiment the NVM device circuit topology can beconfigured as a 2-transistor (2T) memory cell. The 2T-memory cell caninclude a first transistor T₁, a second transistor T₂, a bit line, BL, afirst Wordline, WLW, and a second Wordline, WLR. T₁ can be a metal oxidesemiconductor field effect transistor (MOSFET) and T₂ can be a FeFET. T₁having a T₁-source, a T₁-gate, and a T₁-drain. T₂ having a T₂-source, aT₂-gate, and a T₂-drain. WLW can be configured to receive and/ortransmit a write signal for write operations. WLR can be configured toreceive and/or transmit a read signal for read operations. T₂-drain canbe connected to BL and WLW. T₂-gate can be connected to WLW. T₂-sourcecan be connected to T₁-drain. T₁-gate can be connected to WLR and BL.T₁-source can be connected to ground, GND.

The memory cell can include a plurality of 2T-memory cells arrange in amemory cell array. The memory cell array can include a first 2T-memorycell, a second 2T-memory cell, a third 2T-memory cell, a third 2T-memorycell, a fourth 2T-memory cell, a fifth 2T-memory cell, a sixth 2T-memorycell, a seventh 2T-memory cell, and an eighth 2T-memory cell, eachmemory cell having a T₁ and a T₂, wherein T₁ can be a MOSFET and T₂ canbe a FeFET. The first 2T-memory cell can have a first T₁ and a first T₂.The second 2T-memory cell can have a second T₁ and a second T₂. Thethird 2T-memory cell can have a third T₁ and a third T₂. The fourth2T-memory cell can have a fourth T₁ and a fourth T₂. The fifth 2T-memorycell can have a fifth T₁ and a fifth T₂. The sixth 2T-memory cell 124can have a sixth T₁ and a sixth T₂. The seventh 2T-memory cell can havea seventh T₁ and a seventh T₂. The eighth 2T-memory cell 124 can have aneighth T₁ and a eighth T₂. The memory cell array can include a first BL,BL1, a second BL, BL2, a third BL, BL3, and a fourth BL, BL4. The memorycell array can include a first WLW, WLW1, a second WLW, WLW2, a firstWLR, WLR1, and a second WLR, WLR2, wherein each of WLW1 and WLW2 can beconfigured to receive and/or transmit a write signal for writeoperations, and each of WLR1 and WLR2 can be configured to receiveand/or transmit a read signal for read operations. The first cellT₂-drain can be connected to BL1 and WLW1. The first cell T₂-gate can beconnected to WLW1. The first cell T₂-source can be connected to firstcell T₁-drain. The first cell T₁-gate can be connected to WLR1 and BL1.The first cell T₁-source can be connected to ground, GND. The secondcell T₂-drain can be connected to BL2 and WLW1. The second cell T₂-gatecan be connected to WLW1. The second cell T₂-source can be connected tosecond cell T₁-drain. The second cell T₁-gate can be connected to WLR1and BL2. The second cell T₁-source can be connected to GND. The thirdcell T₂-drain can be connected to BL3 and WLW1. The third cell T₂-gatecan be connected to WLW1. The third cell T₂-source can be connected tothird cell T₁-drain. The third cell T₁-gate can be connected to WLR1 andBL3. The third cell T₁-source can be connected to GND. The fourth cellT₂-drain can be connected to BL4 and WLW1. The fourth cell T₂-gate canbe connected to WLW1. The fourth cell T₂-source can be connected tofourth cell T₁-drain. The fourth cell T₁-gate can be connected to WLR1and BL4. The fourth cell T₁-source can be connected to GND. The fifthcell T₂-drain can be connected to BL1 and WLW2. The fifth cell T₂-gatecan be connected to WLW2. The fifth cell T₂-source can be connected tofifth cell T₁-drain. The fifth cell T₁-gate can be connected to WLR2 andBL1. The fifth cell T₁-source can be connected to GND. The sixth cellT₂-drain can be connected to BL2 and WLW2. The sixth cell T₂-gate can beconnected to WLW2. The sixth cell T₂-source can be connected to sixthcell T₁-drain. The sixth cell T₁-gate can be connected to WLR2 and BL2.The sixth cell T₁-source can be connected to GND. The seventh cellT₂-drain can be connected to BL3 and WLW2. The seventh cell T₂-gate canbe connected to WLW2. The seventh cell T₂-source can be connected toseventh cell T₁-drain. The seventh cell T₁-gate can be connected to WLR2and BL3. The seventh cell T₁-source can be connected to GND. The eighthcell T₂-drain can be connected to BL4 and WLW2. The eighth cell T₂-gatecan be connected to WLW2. The eighth cell T₂-source can be connected toeighth cell T₁-drain. The eighth cell T₁-gate can be connected to WLR2and BL4. The eighth cell T₁-source can be connected to GND.

In at least one embodiment the NVM device circuit topology can beconfigured as a 3-transistor (3T) memory cell. The 3T-memory cell caninclude a first transistor, T₁, a second transistor, T₂, a thirdtransistor T₃, a first bit line, BLW, a second bit line, BLR, a WordlineWrite, WLW, a Wordline Read, WLR, and a Wordline-Readline, WLRL. Each ofT₁ and T₃ can be a metal oxide semiconductor field effect transistor(MOSFET), and T₂ can be a FeFET. T₁ can have a T₁-source, a T₁-gate, anda T₁-drain. T₂ can have a T₂-source, a T₂-gate, and a T₂-drain. T₃ canhave a T₃-source, a T₃-gate, and a T₃-drain. T₁-drain can be connectedto T₂-gate. T₁-gate can be connected to WLW. T₁-source can be connectedto BLW. T₂-drain can be connected to T₃-source. T₂-gate can be connectedto T₁-drain. T₂-source can be connected to WLRW. T₃-drain can beconnected to BLR. T₃-gate can be connected to WLR. T₃-source can beconnected to T₂-drain. At least one of BLW, WLW, and WLRW can beconnected to GND. WLR can be connected to a voltage supply, V_(DD).

In at least one embodiment the NVM device circuit topology can beconfigured as a 3-transistor (3T) memory cell. The 3T-memory cell caninclude a first transistor, T₁, a second transistor, T₂, a thirdtransistor T₃, a bit line, BL, a Wordline Write, WLW, a Wordline Read,WLR, and a Wordline-Readline, WLRL. Each of T₁ and T₃ can be a metaloxide semiconductor field effect transistor (MOSFET), and T₂ can be aFeFET. T₁ can have a T₁-source, a T₁-gate, and a T₁-drain. T₂ can have aT₂-source, a T₂-gate, and a T₂-drain. T₃ can have a T₃-source, aT₃-gate, and a T₃-drain. T₁-drain can be connected to T₂-gate. T₁-gatecan be connected to WLW. T₁-source can be connected to BL. T₂-drain canbe connected to T₃-drain. T₂-gate can be connected to T₁-drain.T₂-source can be connected to WLRW. T₃-drain can be connected toT₂-drain. T₃-gate can be connected to WLR. T₃-source can be connected toBL.

In at least one embodiment the NVM device circuit topology can beconfigured as a backup and restore circuit (B&R circuit). The B&Rcircuit can include a first transistor, M₁, M₁ having an M₁-source, anM₁-gate, and an M₁-drain. The B&R circuit can include a secondtransistor, M₂, M₂ having an M₂-source, an M₂-gate, and an M₂-drain. TheB&R circuit can include a third transistor, M₃, M₃ having an M₃-source,an M₃-gate, and an M₃-drain. The B&R circuit can include a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain. TheB&R circuit can include a first branch can include M₁, M₃, and ground,GND. The B&R circuit can include a second branch can include M₂, M₄, andGND. Each of M₁ and M₂ can be a metal oxide semiconductor field effecttransistor (MOSFET). Each of M₃ and M₄ can be a FeFET. M₁-drain can beconnected to M₃-source. M₁-gate can be connected to a restore signalinput signal and M₂-gate. M₁-source can be connected to GND. M₂-draincan be connected to M₄-source. M₂-gate can be connected to M₁-gate.M₃-drain configured to be connected to a slave latch via the firstbranch. M₃-drain can be connected to M₄-gate, M₄-drain, M₃-gate, and tothe second branch. M₃-gate can be connected to M₄-gate, M₄-drain,M₃-drain, and to the second branch. M₃-source can be connected toM₁-drain. M₄-drain configured to be connected to the slave latch via thesecond branch. M₄-drain can be connected to M₃-gate, M₃-drain, M₄-gate,and to the first branch. M₄-gate can be connected to M₃-gate, M₃-drain,M₄-drain, and to the first branch. M₄-source can be connected toM₂-drain.

In at least one embodiment the NVM device circuit topology can beconfigured as a D-Flip Flop (DFF). The DFF can include a master latch, aslave latch, and a backup and restore circuit (B&R circuit). The masterlatch can include a first master inverter M_(INV1), a second masterinverter, M_(INV2), a third master inverter, M_(INV3), and a mastertransmission gate, M_(GATE). Input of M_(INV1) can be connected to adata input signal, D. Output of M_(INV1) can be connected to input ofM_(INV2). Input of M_(INV2) can be connected to output of M_(INV1).Output of M_(INV2) can be connected to input of M_(INV3). Input ofM_(INV3) can be connected to output of M_(INV2). Output of M_(INV3) canbe connected to input of M_(GATE). Input of M_(GATE) can be connected tooutput of M_(INV3). Output of M_(GATE) can be connected to input ofM_(INV2) and output of M_(INV1). The slave latch can include a firstslave inverter, S_(INV1), a second slave inverter, S_(INV2), a thirdslave inverter, S_(INV3), and a slave transmission gate, S_(GATE). Inputof S_(INV1) can be connected to output of M_(INV2). Input of S_(INV2)can be connected to output of S_(INV1). Output of S_(INV2) can beconnected to input of S_(INV3) and to a data output Q. Input of S_(INV3)can be connected to output of S_(INV2). Output of S_(INV3) can beconnected to input of S_(GATE). Output of S_(GATE) can be connected toinput of S_(INV2) and output of S_(INV1). The B&R circuit can include afirst transistor, M₁, M₁ having an M₁-source, an M₁-gate, and anM₁-drain. The B&R circuit can include a second transistor, M₂, M₂ havingan M₂-source, an M₂-gate, and an M₂-drain. The B&R circuit can include athird transistor, M₃, M₃ having an M₃-source, an M₃-gate, and anM₃-drain. The B&R circuit can include a fourth transistor, M₄, M₄ havingan M₄-source, an M₄-gate, and an M₄-drain. The B&R circuit can include afirst branch having M₁, M₃, and ground, GND. The B&R circuit can includea second branch having M₂, M₄, and GND. Each of M₁ and M₂ can be a metaloxide semiconductor field effect transistor (MOSFET). Each of M₃ and M₄can be a FeFET. M₁-drain can be connected to M₃-source. M₁-gate can beconnected to a restore signal input signal and M₂-gate. M₁-source can beconnected to GND. M₂-drain can be connected to M₄-source. M₂-gate can beconnected to M₁-gate. M₃-drain configured to be connected to a slavelatch via the first branch. M₃-drain can be connected to M₄-gate,M₄-drain, M₃-gate, and to the second branch. M₃-gate can be connected toM₄-gate, M₄-drain, M₃-drain, and to the second branch. M₃-source can beconnected to M₁-drain. M₄-drain configured to be connected to the slavelatch via the second branch. M₄-drain can be connected to M₃-gate,M₃-drain, M₄-gate, and to the first branch. M₄-gate can be connected toM₃-gate, M₃-drain, M₄-drain, and to the first branch. M₄-source can beconnected to M₂-drain. M₃-drain can be connected to output of S_(GATE),output of S_(INV1), and input of S_(INV2). M₄-drain can be connected toinput of S_(INV3), output of S_(INV2), and data output Q.

Further features, aspects, objects, advantages, and possibleapplications of the present invention will become apparent from a studyof the exemplary embodiments and examples described below, incombination with the Figures, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, aspects, features, advantages and possibleapplications of the present innovation will be more apparent from thefollowing more particular description thereof, presented in conjunctionwith the following drawings. Like reference numbers used in the drawingsmay identify like components.

FIG. 1 is an exemplary schematic showing an exemplary device structureof an embodiment of a P-type noncapacitive field effect transistor(NCFET) with externally connected BiFeO3 ferroelectric material.

FIG. 2 is a graph showing an I_(D)−V_(G) hysteresis curve with twostable nonvolatile states at V_(GS)=0 for an embodiment of a NCFET.

FIG. 3 is an exemplary schematic showing polarization switching by thegate voltage for embodiment of a NCFET.

FIG. 4 is a graph showing an I_(D)−V_(G) hysteresis curve around V_(G)=0for an embodiment of a P-type NCFET.

FIG. 5 is an exemplary schematic showing an embodiment of a backup andrestore (B&R) circuit.

FIG. 6 is an exemplary schematic showing an embodiment of a D flip flop(DFF).

FIG. 7 is an exemplary schematic showing an exemplary process flow foran embodiment of the DFF in a backup operation.

FIG. 8 shows an exemplary process flow for an embodiment of the DFF in arestore operation.

FIG. 9 a graph showing transient waveform snapshots of an embodiment ofthe DFF 120 with the CLK period equal to ˜4 ns during normal “Power On”operations. A few nS after power supply goes off, the internal nodes Qand QN were manually pulled down to ground to mimic real scenarios.

FIG. 10 is a graph showing the impact on I_(DS)−V_(GS) curves by varyingferroelectric layer thickness (T_(FE)) (baseline 6 nm) on an embodimentof the NCFET.

FIG. 11 is a graph showing the impact on I_(DS)−V_(GS) curves by ofchanging ferroelectric layer area (A_(FE)) (baseline 100% of 378 nm²) onan embodiment of the NCFET.

FIG. 12 is a graph showing the impact on backup time and restore time byvarying T_(FE) on an embodiment of the NCFET.

FIG. 13 is a graph showing the impact on backup time and restore time byvarying A_(FE) on an embodiment of the NCFET.

FIG. 14 is a graph showing the impact on backup energy and restoreenergy by varying T_(FE) on an embodiment of the NCFET.

FIG. 15 is a graph showing the impact on backup energy and restoreenergy by varying A_(FE) on an embodiment of the NCFET.

FIG. 16 is a graph showing energy-delay performance overhead of anembodiment of a DFF under a supply voltage from 0.30 V to 0.80 V,wherein the kinetic coefficient ρ is 0.25.

FIGS. 17-20 are is graphs showing performance indicators for anembodiment of a DFF in regards to local mismatches in ferroelectriclayer thickness and area in NCFETs used to make the DFF. FIG. 17 is agraph showing the impact on backup latency due to variations, FIG. 18 isa graph showing the impact on backup energy, FIG. 19 is a graph showingthe impact on restore latency, and FIG. 20 is a graph showing the impacton restore energy.

FIG. 21 is a graph showing a sample of power income versus time for atypical VLSI computing system for computation energy, restore energy,and backup energy.

FIG. 22 is a graph showing energy harvesting utilization for aconventional volatile processor and a non-volatile processor.

FIG. 23 is an exemplary schematic showing a set up for a conventionalDFF device.

FIG. 24 is an exemplary schematic showing an exemplary set up for anembodiment of an intrinsic nonvolatile area-efficient DFF device.

FIG. 25 is an exemplary schematic showing an exemplary schematic for anembodiment of an N-type FeFET.

FIG. 26 is an exemplary schematic showing an exemplary schematic for acapacitance network of an embodiment of an N-type FeFET.

FIG. 27 is a graph showing I_(DS)−V_(G) curves demonstratingsteep-switching and hysteresis with the baseline MOSFET curve.

FIG. 28 is a graph showing the effect of tuning ferroelectric negativecapacitance of an embodiment of a FeFET.

FIG. 29 is an exemplary schematic showing an embodiment of a slave latchconfigured with a differential-driving input pair D/DN using N-typeFeFETs.

FIG. 30 is an exemplary schematic showing an embodiment of a slave latchconfigured with a driving input D.

FIG. 31 is a conventional CMOS volatile latch that was used as abaseline to compare to the latch topology of FIG. 29.

FIG. 32 is an exemplary schematic showing a conventional CMOS volatilelatch that was used as a baseline to compare to the latch topology ofFIG. 30.

FIG. 33 is an exemplary schematic showing an exemplary steady stateoperation of the latch topology of FIG. 29.

FIG. 34 is an exemplary schematic showing an exemplary transition stateoperation of the latch topology of FIG. 29.

FIG. 35 is a graph showing transient waveforms for sample and holdoperations with a steady supply for an embodiment of the latch.

FIG. 36 is a graph showing the polarization switching progress for anembodiment of the latch with a higher data-rate.

FIG. 37 is a graph showing transient waveforms with backup and restoreoperations due to power failures for an embodiment of the latch.

FIG. 38 is an exemplary schematic showing an embodiment of a slave latchconfigured with a differential-driving input pair D/DN using P-typeFeFETs.

FIG. 39 is an exemplary schematic showing an embodiment of a slave latchconfigured with a differential-driving input pair D/DN using both N-typeFeFETs and P-type FeFETs.

FIG. 40 is an exemplary schematic illustrating the operating mechanismof the latch topology of FIG. 30 during sampling, showing charging anddischarging routes.

FIG. 41 is an exemplary schematic illustrating the operating mechanismof the latch topology of FIG. 30 in a hold phase, showing charging anddischarging routes.

FIG. 42 is a graph showing the transient simulation waveforms of thelatch topology of FIG. 30.

FIG. 43 is a graph showing energy versus delay comparison between CMOSlatches and embodiments of the latches for ×1 fan-out driving strength.V_(DD) ranges from 1.0V to 0.5V from left to right.

FIG. 44 is a graph showing energy versus delay comparison between CMOSlatches and embodiments of the latches for ×4 fan-out driving strength(only CMOS transistors are increased to ×4). V_(DD) ranges from 1.0V to0.5V from left to right.

FIG. 45 is a graph showing supply voltage as a function of backup timefor an embodiment of a latch.

FIG. 46 is a graph showing supply voltage as a function of restore timefor an embodiment of a latch.

FIG. 47 is a graph showing supply voltage as a function of backup energyfor an embodiment of a latch.

FIG. 48 is a graph showing supply voltage as a function of restoreenergy for an embodiment of a latch.

FIG. 49 is an exemplary schematic showing an embodiment of a DFF withits slave latch replaced with an embodiment of the latch topology ofFIG. 29.

FIG. 50 is an exemplary schematic showing another embodiment of a DFFwith its slave latch replaced with an embodiment of the latch topologyof FIG. 29.

FIG. 51 is an exemplary schematic showing another embodiment of a DFFwith its slave latch replaced with an embodiment of the latch topologyof FIG. 30.

FIG. 52 is an exemplary schematic showing a conventional CMOS DFF forcomparison to an embodiment of the DFF disclosed herein.

FIG. 53 is a graph showing the transient simulation waveforms of anembodiment of the DFF.

FIG. 54 is a graph showing supply voltage as a function of backup energyfor an embodiment of a DFF compared to conventional DFFs.

FIG. 55 is a graph showing supply voltage as a function of restoreenergy for an embodiment of a DFF compared to conventional DFFs.

FIG. 56 is a graph showing supply voltage as a function of backup timefor an embodiment of a DFF compared to conventional DFFs.

FIG. 57 is a graph showing supply voltage as a function of restore timef for an embodiment of a DFF compared to conventional DFFs.

FIG. 58 is a graph comparing the energy versus delay between embodimentsof the DFF and conventional DFF designs.

FIG. 59 is an exemplary schematic showing a simulation setup foranalyzing the impact of V_(TH) variation on an embodiment

FIG. 60 is a graph showing yield simulation results considering V_(TH)variation at different supply voltages for an embodiment of a latch andan embodiment of a DFF.

FIG. 61 is an exemplary schematic showing a schematic for an N-typeFeFET.

FIG. 62 is an exemplary schematic showing a fin-structured FeFET device.

FIG. 63 is a graph showing a typical hysteretic G_(DS)−V_(GS) extractedform one fin of a fin-structured FeFET device at V_(DS)=10 mV.

FIG. 64 is a graph showing an exemplary energy landscape plot for anembodiment of a FeFET.

FIG. 65 is a graph showing static internal states with an embodiment ofthe FeFET biased at V_(GS)=0.

FIG. 66 is an exemplary schematic showing an embodiment of a 2T-memorycell.

FIG. 67 is an exemplary schematic showing the operating status of the2T-memory cell of FIG. 66 in power-off mode and in power-on idle mode.

FIG. 68 is an exemplary schematic showing the operating status of the2T-memory cell 1 of FIG. 66 in voltage-mode read ‘0’ and voltage-moderead ‘1’.

FIG. 69 is an exemplary schematic showing the operating status of the2T-memory cell 1 of FIG. 66 in voltage-mode write ‘0’ and voltage-modewrite ‘1’.

FIG. 70 is a graph showing a snapshot of a SPICE transient simulationwaveform of an embodiment of the memory cell array, showing polarizationstatuses for the FeFET transistors in the array.

FIG. 71 is an exemplary schematic showing an embodiment of a 3T-memorycell having a two-bit line topology and a single-bit line topology.

FIG. 72 is an exemplary schematic showing an embodiment of a 3T-memorycell in write mode using a two-step write method.

FIG. 73 is a graph showing SPICE transient simulation waveforms for anembodiment of the memory cell.

FIG. 74 is an exemplary schematic showing a comparison between supplyvoltage ranges required for write for a conventional memory cell and foran embodiment of the memory cell.

FIG. 75 is a graph showing the simulated write energy per cell versusthe write latency for embodiments of the memory cell, as compared to aconventional memory cell.

FIG. 76 is a graph showing energy and latency for an embodiment of thememory cell as a function of ρ.

FIG. 77 is a graph showing the simulated read energy per cell versusread latency for an embodiment of the memory cell.

FIG. 78 is a graph showing typical 10 nm n-type FeFET G_(DS)−V_(G)curves with over 5 orders of magnitudes in the sensed drain-sourcechannel conductions (G_(DS)) between the bistable ON/OFF nonvolatilestates sensed at zero V_(G).

FIG. 79 is an exemplary schematic showing an embodiment of the 4T B&Rcircuitry.

FIG. 80 is an exemplary schematic showing an embodiment of a DFF with anembodiment of the 4T B&R circuitry.

FIG. 81 is an exemplary schematic showing an embodiment of the DFF in abackup operation.

FIG. 82 is an exemplary schematic showing an embodiment of the DFF 120in a restore operation.

FIG. 83 is a graph showing transient waveforms of an embodiment of theDFF.

FIG. 84 is a graph showing V_(DD) v. backup time for embodiments of theDFF.

FIG. 85 is a graph showing V_(DD) v. backup energy for embodiments ofthe DFF.

FIG. 86 is a graph showing V_(DD) v. restore energy for embodiments ofthe DFF.

FIG. 87 is a graph showing clock to Q energy v. clock to Q delay forembodiments of the DFF.

FIG. 88 is a graph showing the backup time versus backup energy for anembodiment of the DFF and compares it to conventional DFF devices.

FIG. 89 is a graph showing a normal mode energy-delay overhead analysisfor an embodiment of the DFF and compares it to conventional DFFdevices.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of exemplary embodiments that are presentlycontemplated for carrying out the present invention. This description isnot to be taken in a limiting sense, but is made merely for the purposeof describing the general principles and features of the presentinvention. The scope of the present invention is not limited by thisdescription.

Embodiments include nonvolatile a memory (NVM) device 100 that can beconfigured for logic switching and/or digital computing. For example,embodiments of the NVM device 100 can be configured as any one orcombination of a memory cell 124, a D flip flop (DFF) 120, a Backup andRestore circuit (B&R circuit) 116, and/or a latch 118, 122 for a DFF120.

Referring to FIGS. 1-3, in some embodiments, the NVM device 100 caninclude at least one field effect transistor (FET) 102. The FET 102 caninclude a substrate 104 having a drain 106, a source 108, and a gate 110formed thereon. The drain 106, source 108, and gate 110 can be separateby a metal layer 112. Embodiments of the FET 102 can be a ferroelectricFET (FeFET) 102. For example, the FeFET 102 may include a ferroelectriclayer 114 within the gate 110 of the FET 102. It should be noted that aFeFET 102 can be referred to as a negative capacitance or differentialcapacitance FET (NCFET) because its charge decreases as the appliedvoltage increases within a certain voltage range. The FeFET 102 can beconfigured to exhibit a wide current-voltage (I-V) hysteresis coveringzero gate bias. This may be achieved by tuning at least a portion of thethickness of the ferroelectric layer.

Topologies for embodiments of the NVM devices 100 disclosed herein caninclude at least one FeFET 102 configured to have a wide current-voltage(I-V) hysteresis covering zero gate bias. For example, circuittopologies of embodiments of the NVM devices 100 can be configured toexploit the wide hysteresis feature that can be obtained from the use ofan embodiment of the FeFET 102. Embodiments of the FeFET 102 can beconfigured to behave concurrently as a nonvolatile memory and a logicdevice with inherent compatibility with Boolean signaling. These andother features can reduce the complexity and energy consumption of theinterface with logic gates. Additionally, embodiments of the FeFET 102can provide a memory operation without static current during a writeoperation. In some embodiments, the FeFET 102, when used embodiments ofthe NVM devices 100 can be configured to exhibit a steep hysteresis edgeand a high ratio between the two drain-source current states (I_(DS)states) at a gate voltage (V_(G))=0. These two states can be the twolocally stable states shown in FIG. 2. The I-V curve of FIG. 2 wasobtained based on the LK-equation modeling method, with 10 nm predictivetechnology model (PTM) complementary metal-oxide-semiconductor (CMOS)FinFET as the integrated MOSFET. A FinFET is a tri-gate transistor inwhich the gate 110 is formed on at least two sides of the channel 111.The LK-equation coefficients are: alpha=−1.05e9 m/F, beta=1e7m⁵/F/coul², and gamma=6e11 m⁹/F/coul⁴. One state can switch to the otherby applying a sufficiently high-amplitude positive or negative V_(GS)that exceeds the coercive voltage, as shown with an N-type FeFET in FIG.3.

Capacitance matching may be beneficial to obtain the characteristics inFIGS. 2-3. In addition, V_(TH) shifting in the baseline MOSFET can bedone to locate the hysteresis window around V_(G)=0. This can includecentering the hysteresis at V_(G)=0. The shifting of V_(TH) describedherein can be done to generate NVM devices 100 with addednon-volatility, as compared to conventional nonvolatile memory devices.As can be seen in FIG. 4 embodiments of the NVM device 100 can begenerated that provide steep hysteresis edges with a slope below 10mV/decade for above 7 orders in magnitude between the two I_(DS)hysteresis states at V_(G)=0. A steep-slope transition edge can be usedto provide a wide gate voltage range in which the polarization of theNVM device 100 stays stable against noise. In addition, NVM devices 100can be generated with a higher ON-state current and a lower OFF-statecurrent. A higher ON-state current and a lower OFF-state current canlead to faster restore and immunity to device variations.

Embodiments of the NVM device 100 can be configured as a B&R circuit 116and/or a DFF 120 having an embodiment of the DFF 120 as part of itsaccessory circuitry. Such a NVM device 100 can be configured to maintainits state during a power outage and/or during an intermittent powersupply. This can be useful for nonvolatile computing (e.g., preventcomputation progress loss due to either an unexpected or scheduled poweroutage). For example, embodiments of the B&R circuit 116 and/or a DFF120 can be used for backing up memory and DFF states to on-chipnonvolatile memory elements. Nonvolatile computing techniques can alsobe useful for energy harvesting, and in particular energy harvestingwith Internet-of-Things (IoT) applications where frequent check-pointingis generally required under the notoriously intermittent supply providedby energy harvesting mechanisms. Nonvolatile computing techniques, viain situ backup methods, can also provide more energy savings inpower-gating applications (e.g., cut off leakage power for higher energyefficiency).

FIG. 5 shows an embodiment of a B&R circuit 116. The B&R circuit 116 canhave a first transistor, M₁. M₁ can have an M₁-source, an M₁-gate, andan M₁-drain. The B&R circuit 116 can have a second transistor, M₂. M₂can have an M₂-source, an M₂-gate, and an M₂-drain. The B&R circuit 116can have a third transistor, M₃. M₃ can have an M₃-source, an M₃-gate,and an M₃-drain. The B&R circuit 116 can have a fourth transistor, M₄.M₄ can have an M₄-source, an M₄-gate, and an M₄-drain. The B&R circuit116 can have a fifth transistor, M₅. M₅ can have an M₅-source, anM₅-gate, and an M₅-drain. The B&R circuit 116 can have a sixthtransistor, M₆. M₆ can have an M₆-source, an M₆-gate, and an M₆-drain.The B&R circuit 116 can have a seventh transistor, M₇. M₇ can have anM₇-source, an M₇-gate, and an M₇-drain. The B&R circuit 116 can have aneighth transistor, M₈. M₈ can have an M₈-source, an M₈-gate, and anM₈-drain. Any one or combination of the transistors of the B&R circuit116 can be a metal oxide semiconductor field effect transistor (MOSFET)or a FeFET 102.

The B&R circuit 116 can further include a first branch 101 and a secondbranch 103. The first branch 101 can include M₁, M₂, M₅, M₇, and GND.The second branch 103 can include M₃, M₄, M₆, and M₈. Depending on theinputs, either the first branch 101 or the second branch 103 operates asa backup branch or a restore branch. For example, when the first branch101 operates as a backup branch, the second branch 103 operates as arestore branch. When the first branch 101 operates as a restore branch,the second branch 103 operates as a backup branch. Particular noteshould be made to the cross-coupled circuit connection between M₅ andthe second branch 103 and M₆ and the first branch 101. This canfacilitate backup and restore operations in only one step without staticcurrent consumptions.

In some embodiments, the B&R circuit 116 can be connected to a slavelatch 118. (See FIG. 6). This can be done to generate a DFF 120. Forexample, the first branch 101 and the second branch 103 can be connectedto a slave latch 118 to form a DFF 120.

In at least one embodiment, M₁, M₂, M₃, M₄, M₇, and M₈ are MOSFETs. Inat least one embodiment, M₅ and M₆ are FeFETs 102. M₁-gate can beconnected to a backup control signal input, B_(kp_input) and M₃-gate.M₁-drain can be connected to M₂-drain. M₁-drain can be configured to beconnected to a slave latch 118, which can be via the first branch 101.M₁-source can be connected to M₅-source and M₇-drain. M₂-drain can beconnected to M₁-drain. M₂-drain can be configured to be connected to theslave latch 118, which can be via the first branch 101. M₂-gate can beconnected to a backup and restore control signal input, B_(kp)+R_(str)and M₃-gate. M₂-source can be connected to M₆-gate, M₅-drain, M₅-gate,M₆-drain, and M₃-source. M₃-drain can be connected to M₄-drain. M₃-draincan be configured to be connected to the slave latch 118, which can bevia the second branch 103. M₃-gate can be connected to B_(kp)+R_(str)and M₁-gate. M₃-source can be connected to M₅-gate, M₆-drain, M₅-drain,M₂-source, and M₆-gate. M₄-drain can be connected to M₃-drain. M₄-draincan be configured to be connected to the slave latch 118, which can bevia the second branch 103. M₄-gate can be connected to a backup controlsignal output, B_(kp_output). M₄-source can be connected to M₆-sourceand M₈-drain. M₅-drain can be connected to M₂-source, M₅-gate, M₆-gate,M₆-drain, and M₃-source. M₅-gate can be connected to M₃-source,M₆-drain, M₆-gate, M₂-source, and M₅-drain. M₅-source can be connectedto M₇-drain and M₁-source. M₆-drain can be connected to M₃-source,M₅-gate, M₆-gate, M₅-drain, and M₂-source. M₆-gate can be connected toM₂-source, M₅-drain, M₅-gate, M₆-drain, and M₃-source. M₆-source can beconnected to M₄-source and M₈-drain. M₇-drain can be connected toM₁-source and M₅-source. M₇-gate can be connected to a restore inputcontrol signal, R_(str). M₇-source can be connected to ground, GND,which can be via the first branch 101. M₈-drain can be connected toM₄-source and M₆-source. M₈-gate can be connected to M₇-gate. M₈-sourcecan be connected to GND, which can be via the second branch 103.

Referring to FIG. 6, in some embodiments the B&R circuit 116 can be usedto generate a DFF 120. For example, embodiments of the DFF 120 caninclude a master latch 122 and a slave latch 118 in connection with anembodiment of the B&R circuit 116. In some embodiments, the DFF 120 caninclude a master latch 122 and a slave latch 118 in connection with theB&R circuit 116, and be configured for digital computing operations(e.g., backup and restore purposes). In at least one embodiment, theback and restore operations can be associated with the slave latch 118only.

The master latch 122 can have a first master inverter M_(INV1), a secondmaster inverter, M_(INV2), a third master inverter, M_(INV3), and amaster transmission gate, M_(GATE). The input of M_(INV1) can beconnected to a data input signal, D. The output of M_(INV1) can beconnected to the input of M_(INV2). The input of M_(INV2) can beconnected to the output of M_(INV1). The output of M_(INV2) can beconnected to the input of M_(INV3). The input of M_(INV3) can beconnected to the output of M_(INV2). The output of M_(INV3) can beconnected to the input of M_(GATE). The input of M_(GATE) can beconnected to the output of M_(INV3). The output of M_(GATE) can beconnected to the input of M_(INV2) and the output of M_(INV1).

The slave latch 118 can have a first slave inverter, S_(INV1), a secondslave inverter, S_(INV2), a third slave inverter, S_(INV3), and a slavetransmission gate, S_(GATE). The input of S_(INV1) can be connected tothe output of M_(INV2). The input of S_(INV2) can be connected to theoutput of S_(INV1). The output of S_(INV2) can be connected to the inputof S_(INV3) and to a data output Q. The input of S_(INV3) can beconnected to the output of S_(INV2). The output of S_(INV3) can beconnected to the input of S_(GATE). The output of S_(GATE) can beconnected to the input of S_(INV2) and the output of S_(INV1).

A clock driver, CLK can be used to generate an in-phase clock signal, c,and opposite-phase clock signal, cn, for M_(INV1), M_(GATE), S_(INV1),and/or S_(GATE). Embodiments of the CLK can include a first clockinverter, CLK_(INV1), having an output connected to an input of a secondclock inverter, CLK_(INV2). CLK_(INV1) can be configured to generate cn.CLK_(INV2) can be configured to generate c. Each of M_(GATE) andS_(GATE) can be a gate circuit for transmitting or blocking the outputsignal from the master latch 122 or slave latch 118, respectively, inresponse to the clock signal from CLK. For example, the DFF 120 can beconfigured such that each of M_(GATE) and S_(GATE) passes the outputsignal of the master latch 122 or slave latch 118, respectively, whenthe clock signal is HIGH (e.g., M_(GATE) or S_(GATE) becomesconductive). Each of M_(GATE) and S_(GATE) can be configured to blockthe output signal of the master latch 116 or slave latch 118,respectively, when the clock signal is LOW (e.g., M_(GATE) or S_(GATE)becomes non-conductive).

Each of M₁-drain and M₂-drain can be connected to the output ofS_(GATE), the output of S_(INV1), and the input of S_(INV2). Forexample, the first branch 101 can be connected to the output ofS_(GATE), the output of S_(INV1), and the input of S_(INV2). Each ofM₃-drain and M₄-drain can be connected to the input of S_(INV3), theoutput of S_(INV2), and data output Q. For example, the second branch103 can be connected to the input of S_(INV3), the output of S_(INV2),and data output Q.

In some embodiments, when both B_(k) and R_(str) are low, the interfacetransistors (M₁, M₂, M₃, and M₄) between the slave latch 118 and the B&Rcircuit 116 are turned OFF by the gate signal B_(k) and R_(str). Thiscan cause the master latch 122 and slave latch 118 portions of the DFF120 to function the same as a conventional positive-edge triggered DFF.

FIG. 7 shows the DFF 120 circuit state transition in the slave latch 118during a backup operation. In a backup operation, a feedback network isgenerates. For example, when a supply outage is about to come, thebackup control signal B_(kp) becomes high and turns ON the interfacetransistors (M₁, M₂, M₃, and M₄). Note that the pull-down transistors(M₇ and M₈), gated by R_(str), are turned OFF. Using Q=‘1’(corresponding to a high supply voltage, V_(DD)) and QN=‘0’(corresponding to GND), the feedback network quickly biases M₅ and M₆ toswitch to (or maintain) a positive polarization for M₅ and a negativepolarization for M₆, respectively. The polarization switching isstraightforward as the M₅-gate is biased at voltage levels opposite toM₅-drain and M₅-source (e.g, V_(DD)−V_(TH) for a high voltage level andGND at a low level). Additionally, M₆-gate is biased at voltage levelsopposite to M₆-drain and M₆-source terminals (e.g, V_(DD)−V_(TH) for ahigh voltage level and GND at a low level). After the polarizationswitching is accomplished, the removal of V_(DD) (the removal of V_(DD)being a supply outage) will not affect the stored polarization states,regardless of the B_(kp) and R_(str) control signal levels. Note thatthe backup operation does not need to change the polarization if thestate of the previous backup is the same. Operations with Q=‘0’(corresponding to GND) and QN=‘1’ (corresponding to a high supplyvoltage, V_(DD)) would be similar.

FIG. 8 shows the DFF 120 circuit state transition for a restoreoperation. During the entire restore operation, the CLK and B_(kp) areset to be low (C=‘0’ and CN=‘1’), and R_(str) is set to be high. Thiscan guarantee that the slave latch 118 is isolated from the master latch122. As a result, the sensed resistance from node Q and to GND and fromQN to V_(DD) determines the final settled Q and QN voltage levels. Forthe positively polarized FeFET (either M₅ or M₆) its drain-to-sourceresistance is orders of magnitude lower than the other negativelypolarized FeFET (either M₆ or M₅), which leads to a much strongerpull-down effect on the settling of the branch within which M₅ or M₆ islocated. The positive feedback network can further enhance thedifference in magnitude, and finally lead to a full settling down asV_(DD) recovers.

FIG. 9 is a transient waveform snapshot, showing operations of anembodiment of the DFF 120 with a steady V_(DD) and backup and restoreoperations due to power failures. The clock frequency was set to 0.25GHz when the power supply was stable. It should be noted, however, thatthe clock frequency can be much faster because the isolated accessorybackup and restore circuitry has negligible impact on the normaloperation. To prevent the backup and restore operations from beinginterrupted, however, CLK can be kept low. The polarization state, asshown in FIG. 9 remains stable in the power-OFF periods. Thanks to thesimple timing requirement and the small control load, there is no needfor a second supply network to deliver power for the control signals.

It should be noted that embodiments of the DFF 120 and/or B&R circuit116 can be built with P-type transistors connecting to V_(DD) witheffective control signals at a low voltage.

Any one or combination of the parameters of any one or combination ofFeFETs 102 can be tuned by adjusting the thickness, T_(FE), of theferroelectric layer 114 and/or the area, A_(FE), of the ferroelectriclayer 114. Adjusting T_(FE) and/or A_(FE) cab facilitate generating anNVM device 100 with improved energy-delay overhead during normaloperations, improved backup and restore energy and delay, improvedretention time, and improved yield and reliability. Improving the backupand restore energy can be beneficial for NVM devices 100 used inenergy-harvesting systems experiencing intermittent power supplies.Conventional nonvolatile memory devices are limited in improvements tooverall energy efficiency, as more energy spent for backup and restoreoperations generally results in less energy for computation. Forexample, for check-pointing applications, the backup and restore energyindicates a certain period of power-off time (break-even time (BET)),below which no energy savings could be achieved. Improved backup andrestore time can also be beneficial for some applications when a fastresponse is preferred (e.g., fine-time-granularity power-gatingscenarios and fast-response processors).

FIG. 10 shows the impact on I_(DS)−V_(GS) curves by varying T_(FE)(baseline 6 nm) on an embodiment of the FeFET 102. FIG. 11 shows theimpact on I_(DS)−V_(GS) curves by of changing A_(FE) (baseline 100% of378 nm²) on an embodiment of the FeFET 102. FIG. 12 shows the impact onbackup time and restore time by varying T_(FE) on an embodiment of theFeFET 102. FIG. 13 shows the impact on backup time and restore time byvarying A_(FE) on an embodiment of the FeFET 102. FIG. 14 shows theimpact on backup energy and restore energy by varying T_(FE) on anembodiment of the FeFET 102. FIG. 15 shows the impact on backup energyand restore energy by varying A_(FE) on an embodiment of the FeFET 102.In FIGS. 10-15, V_(DD)=0.5V, kinetic coefficient ρ=0.25, alpha=−1.05e9m/F, beta=1e7 m⁵/F/coul², and gamma=6e11 m⁹/F/coul⁴.

FIGS. 10-15 show how changes in T_(FE) and A_(FE) affect the I-Vcharacteristics and the performance of a DFF 120 using an embodiment ofthe FeFET 102. It can be seen that increasing T_(FE) can increase thecoercive voltage or energy barrier to flip the polarization, leading tolonger retention time and more time to switch the polarization. A largerT_(FE) can also reduce the restore time with a higher ON/OFF resistanceratio and a lower ON-state resistance. It can also be seen thatvariation of T_(FE) from 5 nm to 7 nm slightly affects the backup andrestore energy by less than 10%. Meanwhile, decreasing A_(FE) alsochanges the capacitance matching between CFE and CMOS, leading to adifferent I-V with a higher coercive voltage, a lower ON-state current,and longer polarization switching time. Considering the inevitableT_(FE) and A_(FE) variations in the fabrication process, T_(FE) andA_(FE) should be carefully optimized considering the supply voltagerange, the retention model, and the application requirements on theretention time, and backup and restore energy and latency.

A design performance evaluation using SPICE simulations was conductedusing an embodiment of the DFF 120. T_(FE) was set to 6 nm and A_(FE)was set to 378 nm² (equal to 3×fin_width×channel_length) for one fin,for the optimized tradeoff. These parameter values, unless otherwisestated, were be used in the performance evaluation. A physics-basedferroelectric capacitance model in was employed to build FeFETs 102 with10 nm PTM CMOS FinFET as the integrated MOSFET for the simulation. Inthe model, the ferroelectric material was calibrated by experimentalresults of lead zirconium titanate (PZT) films on hafnium oxide (HfO₂)buffer. To reflect different polarization switching speed, in the FeFETmodel, the kinetic coefficient ρ was varied from 0.04 to 0.25. Thebaseline CMOS volatile DFF (a conventional DFF, which is annotated asCMOS DFF in FIG. 16) was optimized with the minimum area and a similarclock-to-Q delay between ‘0’ and ‘1’ outputs (the number of fins forN-type MOS (NMOS) and P-type MOS (PMOS) is 1 and 2, respectively). TheDFFs 120 were simulated with a 2.0 fF load capacitor and 20 ps risingand falling time for D and CLK inputs.

It is contemplated that for DFFs 120 used in practical applications,energy-delay performance would be critical because the DFF 120 wouldstill operate with a steady supply for a large portion of time.Therefore, it is meaningful that the additional acquired non-volatilitydoes not cause high energy-delay overheads. FIG. 16 shows theseoverheads over the baseline CMOS volatile DFF design. Due to thenormally-OFF configuration of the backup and restore circuitry, theenergy-delay product (EDP) overhead is lower than 2.1% for V_(DD)s above0.4 V. If a larger-size baseline DFF is used, this EDP overhead becomeseven more negligible, because the backup and restore circuitry does notneed to be scaled up by the same ratio due to the low (high) OFF-state(ON-state) FeFET resistance. In addition, thanks to the normally-OFFconfiguration, the additional backup and restore operations have littleimpact on the DFF setup time and hold time requirement.

With semiconductor manufacturing, a process corner is adesign-of-experiments technique that refers to a variation offabrication parameters. Process corners represent the extremes of theseparameter variations within which a circuit that has been etched ontothe wafer must function correctly. A circuit running on devicesfabricated at these process corners may run slower or faster thanspecified and at lower or higher temperatures and voltages, but definingbounds of these variations provides a means to measure whether thecircuit is able to function satisfactorily. In order to verify therobustness of a circuit design, corner lots can be fabricated (e.g.,groups of wafers with process parameters adjusted according toextremes), and used for testing. Shmoo plots can be used to identify theboundary limit beyond which a device begins to fail. Corner-lot analysiscan be an effective means of testing in digital electronics. The namingconvention of the process corners includes identifying three processcorners: 1) typical-typical (TT) process corner, the slow-slow (SS)process corner, and a fast-fast (FF) process corner. Existingnonvolatile memory and DFF designs suffer from the non-idealities of thenonvolatile storage devices inside, especially the variations and lowresistance ratio between different states of resistive memory devices.In such approaches, the worst-corner devices often greatly limit theoverall system performance. For example, write pulse duration forconventional devices is much longer than average to ensure high yield,resulting in high energy consumption. Therefore, it is important toanalyze how the DFF 120 performs with FeFET variations.

FIGS. 10-15 demonstrate how embodiments of the DFF 120 behave withglobal T_(FE) and A_(FE) variations (all devices vary from the designtarget by the same amount). FIGS. 17-20 provide more scenarios and dataanalyses to account for local mismatches (i.e., the two FeFETs in oneDFF 120 having different T_(FE)). In FIGS. 17-20, the curves with squareindictors are for three sets of the DFF 120, where the results representoperating in a range of V_(DD) with T_(FE) diverting away from 6 nm by−10% to +5%. The curves with oval indicators are for conventional DFFdevices. The curves with triangle indicators are for conventional ironcapacitive (FeCap) DFF devices. These simulation results show that themajor impact was on the backup latency in low V_(DD) scenarios, whilethe impact on other metrics was comparatively much less significant thanthat brought by a different supply voltage. The impact of additionalnoise that causes a non-zero initial Q/QN voltage opposite to thedesired value was also analyzed through comprehensive simulations. Noiseup to 200 mV was fully tolerable for correct operations, even with theabove mentioned local FeFET mismatches. Such unwanted initial charge atQ or QN will be quickly discharged by the restore branches. Propertiming, the low ON-state and high OFF-state resistance of the FeFETs atdifferent polarization states enable this feature.

The kinetic coefficient ρ affects the polarization switching timesignificantly. Different practical kinetic coefficient values wereadopted in the simulations to reflect different polarization switchingtimes, as shown in Table 1.

TABLE 1 Performance Comparisons between DFF Designs Con- Con- Con-Embodiment ventional ventional ventional of device device device thedisclosed measured simulated simulated* DFF** Tech. size 130 nm 710 nm180 nm 10 nm Voltage 1.5 V 1.0 V 1.8 V 0.3 V-0.8 V Material PZT MJTReRAM 6 nm HfO2, Capacitive PZT device P = 0.04, ρ = 0.10, p = 0.25T_(Backup+Restore) 2.67 μS >10 μS 1.3 μS 277 pS, 583 pS, 1.29 pSE_(Backup+Restore) 2.4 pJ 382 fJ 735 fJ 1.38 fJ Break-Even / 0.83 1.47mS 55.9 nS Time μS@25° C. *The results are for a conventional topologyDFF of operating at 0.8 V supply (rise to 2.4 V for ReRAM write) for theshortest break-even time. **Backup and restore performance in this tableis simulated at 0.5 V supply. MJT = multi-junction technology ReRAM =resistive Random Access Memory

The data in FIGS. 17-20 show a comparison of the backup and restoreperformance of the DFF 120 with conventional DFF designs. The graphsshow that the DFF 120 exhibits more than 6.0× reduction in the restoreenergy and 30× reduction in the backup energy. The DFF 120 also performsbetter in backup latency, and significantly outperforms the others withmore than 50% reduction in restore latency. In addition, the DFF 120works with general DFFs based on master-slave latch topologies, which issuperior to a design that only works when the baseline DFF has set/resetports. During restore operations, conventional DFF designs could notfully eliminate the static current when the FeFET of that DFF was in thelow-resistance state. The improvement with the DFF 120 stem from thedeeply embedded logic-in-memory operation due to the simple circuitstructure that can carry out the backup and restore operations in onlyone step without static current consumptions.

Table 1 also summarizes the DFF 120 overall performance in comparisonwith the conventional designs. One of the strongest advantages of theDFF 120 over conventional designs is the orders of magnitude lowerenergy for backup and restore operations. Such energy savings partlycome from the capability of FeFETs 102 to operate effectively at a lowervoltage. Two more important factors are: (a) the fundamentally different3-terminal FeFET device operating in a novel cross-coupled circuitrythat avoids static FeFET drain-source current during backup and restoreoperations; (b) FeFETs of a small size that can still ensure fast androbust operations with a high ON/OFF state resistance ratio even in thepresence of significant local and global variations. In contrast,existing resistive memory elements in conventional DFF designs arecontinuously drawing current (because of their inherent two-terminaldevice feature) for a long period of time to ensure yield (because ofrequired-write-time duration variations with a much lower resistanceratio). For capacitive nonvolatile memory devices, their powerinefficiency arises from a complex access interface and a largecapacitance value. The low-energy backup and restore operations in theDFF 120, however, enables higher-efficiency nonvolatile computingapplications. For energy harvesting systems with an intermittent supply,the saved backup and restore energy could be used for computing, leadingto more forward progress and higher quality of service (QoS). Forgeneral power-gating systems, the lower backup and restore energy leadsto a shorter break-even time (BET) versus the leakage energy of an idleunit, indicating significant expansion of opportunity for energy savingsfrom fine-grained power-gating.

As noted herein, FeFETs 102, exhibiting steep-switching capability at alow voltage and the associated benefits for implementingenergy-efficient Boolean logic, can be exploited to generate embodimentsof the B&R circuit 116 and/or embodiments of the DFF 120. Embodiments ofthe DFF 120 consumes negligible static current in backup and restoreoperations, and remains robust even with significant global and localferroelectric material variations across a wide 0.3 V-0.8 V supplyvoltage range, allowing the DFF 120 to achieve energy-efficient andlow-latency backup and restore operations. Embodiments of the DFF 120can have an ultra-low energy-delay overhead, below 2.1% in normaloperations, and can operate using the same voltage supply as the Booleanlogic elements with which it connects. This can facilitateenergy-efficient nonvolatile computing in energy-harvesting andpower-gating applications.

Embodiments of the NVM device 100 can be configured as a latch 118, 122.For example, any of the slave latches 118 and/or master latches 122 caninclude an embodiment of the FeFET 102 to provide an embeddedlogic-in-memory operation (i.e., an intrinsic nonvolatile area-efficientlatch). Embodiments of the latch 118, 122 can be used to provide animproved DFF 120.

For example, conventional on-chip state backup solutions for DFF have abottleneck of significant energy and/or latency penalties that can limitoverall energy efficiency and computing progress. In addition, existingtechniques generally rely on external controls that can limitcompatibility and increases system complexity. Accordingly, advancementsin nonvolatile computing can be achieved by use of an embodiment of anintrinsic nonvolatile area-efficient latch 118, 122 and/or DFF 120. Someembodiments of the latch 118, 122 and/or DFF 120 can be designed usingembodiments of the FeFET 102. Some embodiments of the NVM device 100using an embodiment of the latch 118, 122 and/or an embodiment of theDFF 102 can operate to consume fJ-level energy and ns-level intrinsiclatency for a backup plus restore operation (e.g., 2.4 fJ in energy and1.1 ns in time for a DFF 120 with a supply power of 0.80V).

Scheduled power-gating of very large scale integration (VLSI) computingsystems has been widely adopted in both low-power portable devices andhigh-performance cloud server centers to cut off static leakage power.With such systems states of the registers and flip-flops in thepipelining logic should be backed up to prevent loss of computationstatus if the supply is removed. Similarly, mandatory state backup andrestore operations can be required for battery-less portable devicespowered by energy-harvesting techniques. This is because the ambientenergy sources, such as vibration, photovoltaics, and radio, areessentially intermittent even with sophisticated design methods. FIG. 21shows a sample of power income versus time for a typical VLSI computingsystem for computation energy, restore energy, and backup energy. Thepower outage failures have a strong impact on the computation progressand the overall energy efficiency of IoT computing. On the one hand, thecomputing system will lose its computation states if these states arenot successfully backed up before the power failure. With conventionalsystems, even when techniques of check-pointing are applied to reducethe chance of progress loss, significant overheads of energy and latencystill exist for each backup and restore operation. (See FIG. 22). If thebackup data are stored into out-of-chip nonvolatile memory, huge energyand latency are noticeable, mainly caused by the long-distance datatransmission and constrained parallelism. It is also noted that,although a larger energy storage capacitor buffer can be used to smooththe power trace, it cannot reduce the amount of energy for each backupor restore operation. A larger capacitor also results in larger leakagecurrent and more accumulating time to respond till it reaches anappropriate voltage level for supply regulation.

Embedding nonvolatile memory (NVM) into the same chip can improvenonvolatile processing (NVP) by generated a DFF 120 configured to backup the computation states of each DFF into a local on-chip NVM. Table 2summarizes some existing DFF designs based on ferroelectric capacitordevices, MTJ devices, ReRAM devices, and compares the pros and consagainst an embodiment of the DFF 120. If distributed NVM cells andinterface circuitry are placed close to each DFF to build a nonvolatileDFF for local parallel backup, as illustrated in FIG. 23, thebackup/restore operation will be much faster but still consume highenergy because of the duplicated interface circuit between the DFF andNVM cells. The high current one nonvolatile DFF backup/restore operationalso limits the plausible parallelism.

TABLE 2 Performance Comparison of Conventional DFF Designs to anEmbodiment of an Intrinsic Nonvolatile Area-efficient DFF DeviceEmbodiment Conventional DFF Devices of the DFF Year 2014 2014 2014 20132016 2018 Feature size 130 nm 130 nm 45 nm 180 nm 10 nm 10 nmNonvolatile PZT PZT MTJ Al/TiO₂/Al NCFET with HfO₂ and materialCapacitor Capacitor ReRAM PZT Retention 10 hours to 10 ~10 years ~10years Same as PZT capacitor in Time years; varying by design theoryEndurance Vaiying by matenal; >10¹⁵ 10⁵-10¹⁰; Same as PZT capacitor inpossibly >10₁₅ 10¹⁵ by 2014 theory Voltage 1.5 V 1.5 V 1.1 V 1.8 V 0.4V-0.8 V 0.4 V-1.0 V Area overhead 64% 49% −2% — 35% 25% more transistorsBackup time 1.64 μs 2.22 μs 909 ps  10 ns @ 2.4 V 1.4 ns @ 0.5 V 1.0 ns@ 0.8 V Restore time 1.25 μs 2.2 μs 177 ps 1.3 μs @ 0.4 V  75 ps @ 0.5 V 56 ps @ 0.8 V Backup energy 2.4 pJ 3.44 pJ 82.2 fJ 735 fJ 7.0 fJ @ 0.5V 1.3 fJ @ 0.8 V Restore energy 2.34 pJ in total — 735 fJ 9.0 fJ @ 0.5 V1.1 fJ @ 0.8 V Additional Needed Needed Needed Needed Needed Not NeededControl

In addition, backup and restore control for distributed NV-DFFs canrequire additional wiring with more area and energy consumption. Inaddition, the processor architecture and the software needed to adapt tothe control limits the compatibility of existing software and makes theoperating system or processor design complicated. Furthermore, a backuptriggered too early or too late will waste energy that could otherwisebe saved, or result in a backup failure and rolling back in progress.These problems with conventional DFF devices are exacerbated due to theinherent nature of intermittency and unpredictability in ambient powersources.

As will be explained in detail, embodiments of the latches 118, 122 andDFFs 120 disclosed herein can be configured to have only a few extratransistors added to a conventional CMOS design, leading to a compactcell design. No additional circuitry or a different supply voltage isneeded for sensing or driving functions, as would otherwise be necessaryfor conventional DFFs. In addition, embodiments of the latches 118, 122and DFFs 120 can be free from external backup and restore controlsbecause all backup and restore operations are carried out autonomously.This can improve compatibility and reduce complexity of existing logicdesigns with drop-in replacement of latches and DFFs, as shown in FIG.24. Obviating external controls can significantly reduce the controloverhead for check-pointing and power-gating.

Embodiments of the disclosed latches 118, 122 and DFFs 120 can be fastand energy-efficient, with similar delay and energy consumption toconventional volatile designs under a stable supply. Typical energy andlatency for a backup plus restore operation are only at levels of fJ andns, respectively. Note that the restore time also depends on the supplyvoltage recovery time. The operations could be even faster with kineticcoefficient improvement in the FeFET 102. With such a low energy anddelay overhead, the utilization of harvested energy for the purpose ofcomputing can be significantly improved. For the same reason,check-pointing and power-gating can be carried out in fine grain asneeded with significantly reduced energy and delay penalties.

Many ferroelectric materials, such as PbTiO, BaTiO, Pb(ZrTi)O, HfZrO,etc., can be used to generate an embodiment of the FeFET 102. FIGS.25-27 illustrates a simplified concept for an embodiment of the FeFET102 with the negative capacitor connected to the internal MOSFET gatecapacitor. One interesting phenomenon that fits well with Boolean logiccomputation is the boosted voltage change ΔV_(MOSFET) at the internalMOSFET gate induced by an external FeFET gate voltage change ΔV_(NCFET)with |C_(FE)|>C_(MOS), in which C_(FE) and C_(MOS) represent theferroelectric negative capacitance and the MOSFET gate capacitance,respectively. The voltage gain at the internal MOSFET gate over theoverall applied NCFET gate voltage could be approximated byG=ΔV_(MOSFET)/ΔV_(NCFET)=C_(FE)/(C_(FE)+C_(MOS))=|C_(FE)|/(|C_(FE)|−C_(MOS))>1.This indicates a steep switching that enables a lower supply to achievethe same ON-OFF ratio, as shown in FIG. 27. Tuning C_(FE), so that|C_(FE)|<C_(MOS) within some voltage range, the hysteresis loop in theI_(DS)−V_(GS) can be made to expand to the negative V_(GS) range. (SeeFIG. 28). The mechanism behind this is the polarization P versuselectric-field E hysteresis of the ferroelectric capacitor shown FIG.28. The charge Q_(FE) of the ferroelectric capacitor is a function of Eand P in the way of Q_(FE)=εE+P, where ε is the permittivity of thevacuum, and P is typically >>εE. The switching of P is electricallydetermined by E and a switching occurs when the applied voltage exceedsthe coercive voltage. Before the polarization switching occurs, C_(FE)is positive. As V_(NCFET) increases from 0V to close to the IDS−VGSrising edge, the voltage across the ferroelectric material V increasesfrom the initial value of 0 to close to the coercive voltage. AsV_(NCFET) further increases, V_(FE) steps beyond the coercive voltage,and C_(FE) becomes negative, leading to the unstable negative totalseries capacitance of C_(FE) and C_(MOS) that triggers a very steepswitching of I_(DS) until C_(FE) settles to be positive again. Theoutbound trip is similar. In both outbound and inbound curves away fromthe switching edges, a relatively flat I_(DS)−V_(GS) may be observed ifC_(FE) (being positive in this region) is much smaller than C_(MOS),because ΔV_(MOS)=ΔV_(NCFET)×C_(FE)/(C_(FE)+C_(MOS))≈0. Such a hysteresisfeature covering V_(GS)=0V indicates a stable remnant polarization whenpower is removed. Actually, a zero-polarization of the ferroelectricmaterial is not stable as the free energy is not the lowest. It is alsonoted that the hysteresis width is a function of the dynamics of bothC_(FE) and C_(MOS), and could be typically tuned by varying theferroelectric layer thickness, as observed in FIGS. 27 and 28.

Referring to FIG. 29, in at least one embodiment, the latch can beconfigured as a latch 118, 120 that may be used to form an embodiment ofa DFF 120. In one embodiment, the latch 118, 122 can be configured witha differential-driving input pair D/DN, as shown in FIG. 29. The latch118, 122 can have a first transistor, M₁. M₁ can have an M₁-source, anM₁-gate, and an M₁-drain. The latch 118, 122 can have a secondtransistor, M₂. M₂ can have an M₂-source, an M₂-gate, and an M₂-drain.The latch 118, 122 can have a third transistor, M₃. M₃ can have anM₃-source, an M₃-gate, and an M₃-drain. The latch 118, 122 can have afourth transistor, M₄. M₄ can have an M₄-source, an M₄-gate, and anM₄-drain. The slave latch 118 can have a fifth transistor, M₅. M₅ canhave an M₅-source, an M₅-gate, and an M₅-drain. The latch 118, 122 canhave a sixth transistor, M₆. M₆ can have an M₆-source, an M₆-gate, andan M₆-drain. The latch 118, 122 can have a seventh transistor, M₇. M₇can have an M₇-source, an M₇-gate, and an M₇-drain. The latch 118, 122can have an eighth transistor, M₈. M₈ can have an M₈-source, an M₈-gate,and an M₈-drain. Any one or combination of the transistors of the slavelatch 118 can be a metal oxide semiconductor field effect transistor(MOSFET) or a FeFET 102.

In at least one embodiment, M₁, M₂, M₃, M₄, M₇, and M₈ are MOSFETs. Inat least one embodiment, M₅ and M₆ are FeFETs 102. M₁-drain can beconnected to M₃-gate, M₃-source, M₄-source, M₄-gate, data output Q,M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate,and M₈-gate. M₁-gate can be connected to a clock driver CLK. M₁-sourcecan be connected to a data input D. M₂-drain can be connected toM₃-gate, M₃-source, M₄-source, M₄-gate, data output Q, M₁-drain,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. M₂-gate can be connected to M₁-gate. M₂-source can be connectedto a data input DN. M₃-drain can be connected to a voltage supplyV_(DD). M₃-gate can be connected to M₃-source, M₄-source, M₄-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data outputQN, M₆-drain, M₆-gate, and M₈-gate. M₃-source can be connected toM₃-gate, M₄-source, M₄-gate, data output Q, M₁-drain, M₂-drain, M₅-gate,M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate.M₄-drain can be connected to V_(DD). M₄-gate can be connected toM₃-source, M₄-source, M₃-gate, data output Q, M₁-drain, M₂-drain,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. M₄-source can be connected to M₃-source, M₄-gate, M₃-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data outputQN, M₆-drain, M₆-gate, and M₈-gate. M₅-drain can be connected toM₄-source, M₃-source, M₄-gate, M₃-gate, data output Q, M₁-drain,M₂-drain, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate,and M₈-gate. M₅-gate can be connected to M₄-source, M₃-source, M₄-gate,M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-drain, M₇-gate, M₅-drain,data output QN, M₆-drain, M₆-gate, and M₈-gate. M₅-source can beconnected to M₇-drain. M₆-drain can be connected to M₄-source,M₃-source, M₄-gate, M₃-gate, data output Q, M₁-drain, M₂-drain, M₅-gate,M₇-gate, M₅-drain, data output QN, M₅-drain, M₆-gate, and M₈-gate.M₆-gate can be connected to M₄-source, M₃-source, M₄-gate, M₃-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₇-gate, M₅-drain, data outputQN, M₅-drain, M₆-drain, and M₈-gate. M₆-source can be connected toM₈-drain. M₇-drain can be connected to M₅-source. M₇-gate can beconnected to M₆-gate, M₄-source, M₃-source, M₄-gate, M₃-gate, dataoutput Q, M₁-drain, M₂-drain, M₅-gate, M₅-drain, data output QN,M₅-drain, M₆-drain, and M₈-gate. M₇-source can be connected to GND.M₈-drain can be connected to M₆-source. M₈-gate can be connected toM₇-gate, M₆-gate, M₄-source, M₃-source, M₄-gate, M₃-gate, data output Q,M₁-drain, M₂-drain, M₅-gate, M₅-drain, data output QN, M₅-drain, andM₆-drain. M₈-source can be connected to GND.

Referring to FIG. 30, in at least one embodiment, the latch 118, 122 canbe configured as a latch 118, 122 that may be used to form an embodimentof a DFF 120. The latch 118, 122 can be configured with an input D, asshown in FIG. 30. With the topology of FIG. 30, M₇ and M₈ can have alower V_(TH) for higher yield. The latch 118, 122 can have a firsttransistor, M₁. M₁ can have an M₁-source, an M₁-gate, and an M₁-drain.The latch 118, 122 can have a second transistor, M₂. M₂ can have anM₂-source, an M₂-gate, and an M₂-drain. The latch 118, 122 can have athird transistor, M₃. M₃ can have an M₃-source, an M₃-gate, and anM₃-drain. The latch 118, 122 can have a fourth transistor, M₄. M₄ canhave an M₄-source, an M₄-gate, and an M₄-drain. The latch 118, 122 canhave a fifth transistor, M₅. M₅ can have an M₅-source, an M₅-gate, andan M₅-drain. The latch 118, 122 can have a sixth transistor, M₆. M₆ canhave an M₆-source, an M₆-gate, and an M₆-drain. The latch 118, 122 canhave a seventh transistor, M₇. M₇ can have an M₇-source, an M₇-gate, andan M₇-drain. The latch 118, 122 can have an eighth transistor, M₈. M₈can have an M₈-source, an M₈-gate, and an M₈-drain. The latch 118, 122can have a ninth transistor, M₉. M₉ can have an M₉-source, an M₉-gate,and an M₉-drain. The latch 118, 120 can have a tenth transistor, M₁₀.M₁₀ can have an M₁₀-source, an M₁₀-gate, and an M₁₀-drain. The latch118, 122 can have an eleventh transistor, M₁₁. M₁₁ can have anM₁₁-source, an M₁₁-gate, and an M₁₁-drain. The latch 118, 122 can have atwelfth transistor, M₁₂. M₁₂ can have an M₁₂-source, an M₁₂-gate, and anM₁₂-drain. The latch 118, 122 can have a thirteenth transistor, M_(5b).M_(5b) can have an M_(5b)-source, an M_(5b)-gate, and an M_(5b)-drain.The latch 118, 122 can have a fourteenth transistor, M_(6b). M_(6b) canhave an M_(th)-source, an M_(6b)-gate, and an M_(6b)-drain. Any one orcombination of the transistors of the slave latch 118 can be a metaloxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

In at least one embodiment, M₁, M₂, M₃, M₄, M₇, M₈, M₉, M₁₀, and M₁₁ areMOSFETs. In at least one embodiment, M₅ and M₆ are FeFETs 102. M₁-draincan be connected to M₂-drain and data input D. M₁-gate can be connectedto a clock driver CLK. M₁-source can be connected to M₂-source, M₃-gate,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain. M₂-drain can be connected toM₁-drain and data input D. M₂-gate can be connected to CLK. M₂-sourcecan be connected to M₁-source, M₃-gate, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain. M₃-drain can be connected to V_(DD). M₃-gate can beconnected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain. M3-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-gate, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain. M₄-drain can be connected toV_(DD). M₄-gate can be connected to data output QN, data output Q,M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₆-drain. M₄-source can be connected to data outputQN, data output Q, M₆-gate, M₈-gate, M₄-gate, M₉-drain, M₁₀-drain,M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₅-drain can beconnected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M_(5b)-drain. M5-gatecan be connected to M₁-source, M₂-source, M₅-drain, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M_(5b)-gate, andM_(5b)-drain. M₅-source can be connected to M₇-drain. M_(5b)-drain canbe connected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M₅-drain. M_(5b)-gatecan be connected to M₅-gate. M_(5b)-source can be connected to GND.M₆-drain can be connected to data output QN, data output Q, M₆-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₄-gate. M₆-gate can be connected to data output QN,data output Q, M₆-drain, M_(6b)-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₄-gate. M₆-sourcecan be connected to M₈-drain. M_(6b)-drain can be connected to dataoutput QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M₄-gate, and M₆-drain. M_(6b)-gate canbe connected to M₆-gate. M_(6b)-source can be connected to GND. M₇-draincan be connected to M₅-source. M₇-gate can be connected to M₁-source,M₂-source, M₅-gate, M₅-drain, M₁₁-source, M₁₂-source, M₃-source,M₉-source, M₁₀-source, and M_(5b)-drain. M₇-source can be connected toGND. M₈-drain can be connected to M₆-source. M₈-gate can be connected todata output QN, data output Q, M₆-gate, M₄-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₈-sourcecan be connected to GND. M₉-drain can be connected to data output QN,data output Q, M₆-gate, M₈-gate, M₄-source, M₄-gate, M₁₀-drain,M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₉-gate can beconnected to V_(DD). M₉-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₅-drain,M₁₀-source, and M_(5b)-drain. M₁₀-drain can be connected to data outputQN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₄-gate,M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₁₀-gate can beconnected to GND. M₁₀-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₅-drain, and M_(5b)-drain. M₁₁-drain can be connected to data outputQN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain,M₄-gate, M₁₂-drain, M_(6b)-drain, and M₆-drain. M₁₁-gate can beconnected to CLK. M₁₁-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₅-drain, M₁₂-source, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain. M₁₂-drain can be connected to data outputQN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain,M₁₁-drain, M₄-gate, M_(6b)-drain, and M₆-drain. M₁₂-gate can beconnected to CLK. M₁₂-source can be connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₅-drain, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain.

FIG. 31 is a conventional CMOS volatile latch that was used as abaseline to compare to the latch topology of FIG. 29. FIG. 32 is aconventional CMOS volatile latch that was used as a baseline to compareto the latch topology of FIG. 30. As will be explained herein, theconventional volatile latches behave differently in area, energy perswitching, delay, etc. When the power supply is steady, the logicaltransfer function for each of them is the same, as shown in Table 3. Thelatch 118, 122 of FIG. 29 has two extra N-type FeFETs over the CMOScounterpart design. Both latches are designed with sufficient inputdriving strength so as to overwrite the state by the input pair D/DNdirectly, when the clock signal CLK is high. When CLK is high, itconnects the input differential signals D and DN to the output ports ofQ and QN, respectively.

TABLE 3 Function Table for Latch Topologies of FIGS. 29-32 ScenariosOperations VDD = ‘1’; CLK = ‘1’ Q follows D VDD = ‘1’; CLK = ‘0’ Q holdsVDD = ‘0’ Q = 0 VDD = ‘0’→‘1’; CLK = ‘0’ Q restores to stored state(NV-Latch)

FIG. 33 shows an exemplary steady state operation of the latch topologyof FIG. 29 with CLK being high, using Q as logically ‘1’ (representingV_(DD) in voltage) and QN as logically ‘0’ (representing GND involtage). Controlled by Q or QN, M₃ and Mg are turned OFF, and M₄ and M₇are turned ON. For M₅, its gate voltage is high, and the drainconnecting to QN is low, its source is discharged to GND by M₇. As aresult, M₅ is turned ON and stays at the positive polarization statewith low drain-source resistance. For M₆, it stays OFF at the negativepolarization state with high drain-source resistance. It is noted that,a low voltage of GND at QN will turn OFF M₈, and set M₆ as negativelypolarized (high drain-source resistance): if M₆ was at a previouspositive polarization (low drain-source resistance) state, M₆ sourcewould be charged to Q, which is V_(DD), by M₆. As a result, thedrain-source voltage of M₆ becomes −V_(DD). After that, M₆ will remainnegative in its polarization even if its source node is slowlydischarged by M₈.

FIG. 35 shows the transient waveforms for an embodiment of a latchtopology shown in FIG. 29 for sample and hold operations with a steadysupply. The last P plot indicates “polarization” of the M₅ and M₆. Attime t1 around 61 ns, when the input D is steadily ‘1’, the rising CLKturns ON the switches and the latch output Q switches from the previousstate of ‘0’ to follow the input D with ‘1’, along with the observablepolarization switching of M₅ and M₆. At time t2 around 62 ns, the clockCLK turns to ‘0’ and the latch holds the state even if D changes. Attime t3 around 62.5 ns, the polarization switching is accomplished andstays stable until the latch samples the next different input state.

In FIG. 35, all polarization switching could successfully finish beforethe next switching due to sufficient time window before the nextswitching event. In FIG. 36, with the given input pattern of D and CLK,the duration of the total time of Q to stay at the new state (i.e., ‘1’from 60 ns to 67 ns) is too short for the polarization switching tofinish. FIG. 36 shows the polarization switching progress for anembodiment of the latch with a higher data-rate. The last P plotindicates “polarization” of M₅ M6 for an embodiment of a latch topologyshown in FIG. 29. As can be seen from FIG. 36, none of them in this 7 nsperiod of time succeeds in switching the polarization state, until after67 ns when Q stays at ‘1’ for more than 0.5 nS. Such a phenomenon of apolarization switching speed being lower than the input data rateactually reveals the possibility of having a pseudo-floating ‘0’ of Q atthe latch output, with high resistance to V_(DD) (with turned-OFF PMOS)and also medium-to-high resistance to GND (due to partially turned-OFFFeFET in series with a turned-on NMOS). Note that a pseud-floating ‘1’does not exist because a Q output of ‘1’ is always securely connected toV_(DD) by the PMOS.

The pseudo-floating ‘0’ has three major effects. First, functionalitywill stay correct with proper noise shielding. This is because a shortperiod of ns in time of being pseudo-floating will not have the statecorrupted if external coupling noise is properly isolated. For example,most standard embedded dynamic random access memory (DRAM) cells have aretention time of a few microseconds at the internal floating MOSFETgate. After the polarization switching finishes in the order of ns orsub-ns, this pseudo-floating ‘0’ becomes a steady ‘0’ connecting to GND.Second, endurance will improve. Although existing research has not yetfound out a fundamental bottleneck in improving the endurance or agingeffects of ferroelectric materials, existing ferroelectric materialsdegrade faster in terms of number of full-swing switching cycles thanCMOS transistors. The way above of slower polarization switching helpsto reduce the number of full-swing switching activities, which improvesthe endurance of FeFETs. Third, delay and energy performance may alsoimprove. First, considering the conventional volatile CMOS latch in FIG.31, in order to overwrite the previous ‘0’ state of Q to be ‘1’, the newinput datum of ‘1’ has to “fight” with the pulling down transistor inthe latch. Such a racing condition causes significant power consumptionuntil the switching completes. On the contrary, with the latch topologyof FIG. 29, considering the pseudo-floating ‘0’ Q due to the higherresistance from Q to GND through the not-fully-ON FeFET, overwritingthis ‘0’ to be ‘1’ has less short current or racing conditions, whichimproves the speed and energy performance. It is also noted that, usinga high threshold NMOS transistor could also mitigate the racing “fight”but could not provide equally low pull-down resistance after thepolarization switching finishes.

FIG. 37 shows the transient waveforms with backup and restore operationsdue to power failures for the latch topology of FIG. 29. At around 180nS and 2,175 ns, backup of ‘0’ and ‘1’ is carried out, respectively; ataround 2,100 ns and 4,080 ns, restore of ‘0’ and ‘1’ is observed,respectively. The simulation is accompanied with close to a 2 nspower-down window to mimic really field scenarios.

The latch topology shown in FIG. 29 utilizes N-type FeFETs 102. It iscontemplated to use P-type FeFETs 102 (see FIG. 38), or both N-typeFeFETs 102 and P-type FeFETs 102 (see FIG. 39). The operations of suchlatch topologies would be similar.

Referring to FIG. 38, the latch 118, 122 can have a first transistor,M₁. M₁ can have an M₁-source, an M₁-gate, and an M₁-drain. The latch118, 122 can have a second transistor, M₂. M₂ can have an M₂-source, anM₂-gate, and an M₂-drain. The latch 118, 122 can have a thirdtransistor, M₃. M₃ can have an M₃-source, an M₃-gate, and an M₃-drain.The latch 118, 122 can have a fourth transistor, M₄. M₄ can have anM₄-source, an M₄-gate, and an M₄-drain. The latch 118, 122 can have afifth transistor, M₅. M₅ can have an M₅-source, an M₅-gate, and anM₅-drain. The latch 118, 122 can have a sixth transistor, M₆. M₆ canhave an M₆-source, an M₆-gate, and an M₆-drain. The latch 118, 122 canhave a seventh transistor, M₇. M₇ can have an M₇-source, an M₇-gate, andan M₇-drain. The latch 118, 122 can have an eighth transistor, M₈. M₈can have an M₈-source, an M₈-gate, and an M₈-drain. Any one orcombination of the transistors of the slave latch 118 can be a metaloxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

In at least one embodiment, M₁, M₂, M₃, M₄, M₇, and M₈ are MOSFETs. Inat least one embodiment, M₅ and M₆ are FeFETs 102. M1-drain can beconnected to data input D. M₁-gate can be connected to CLK. M₁-sourcecan be connected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate. M₂-drain can be connected to data input DN.M₂-gate can be connected to M₁-gate. M₂-source can be connected toM₅-gate, M₃-gate, M₅-source, M₁-source, M₇-gate, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₃-drain can be connected to V_(DD). M₃-gate can be connected toM₅-gate, M₁-source, M₅-source, M₂-source, M₇-gate, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₃-source can be connected to M₅-drain. M₄-drain can be connected toV_(DD). M₄-gate can be connected to M₅-gate, M₃-gate, M₅-source,M₂-source, M₇-gate, M₇-drain, data output Q, data output QN, M₆-source,M₈-drain, M₈-gate, M₆-gate, and M₁-source. M₄-source can be connected toM₆-drain. M₅-drain can be connected to M₃-source. M5-gate can beconnected to M₁-source, M₃-gate, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate. M₅-source can be connected to M₅-gate, M₃-gate,M₁-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate. M₆-drain can beconnected to M₄-source. M₆-gate can be connected to M₅-gate, M₃-gate,M₅-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₁-source, and M₄-gate. M₆-source can beconnected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain,data output Q, data output QN, M₁-source, M₈-drain, M₈-gate, M₆-gate,and M₄-gate. M₇-drain can be connected to M₅-gate, M₃-gate, M₅-source,M₂-source, M₇-gate, M₁-source, data output Q, data output QN, M₆-source,M₈-drain, M₈-gate, M₆-gate, and M₄-gate. M₇-gate can be connected toM₅-gate, M₃-gate, M₅-source, M₂-source, M₁-source, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate.M₇-source can be connected to GND. M₈-drain can be connected to M₅-gate,M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain, data output Q, dataoutput QN, M₆-source, M₁-source, M₈-gate, M₆-gate, and M₄-gate. M₈-gatecan be connected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₁-source,M₆-gate, and M₄-gate. M₈-source can be connected to GND.

Referring to FIG. 39, the latch 118, 122 can have a first transistor,M₁. M₁ can have an M₁-source, an M₁-gate, and an M₁-drain. The latch118, 122 can have a second transistor, M₂. M₂ can have an M₂-source, anM₂-gate, and an M₂-drain. The latch 118, 122 can have a thirdtransistor, M₃. M₃ can have an M₃-source, an M₃-gate, and an M₃-drain.The latch 118, 122 can have a fourth transistor, M₄. M₄ can have anM₄-source, an M₄-gate, and an M₄-drain. The latch 118, 122 can have afifth transistor, M₅. M₅ can have an M₅-source, an M₅-gate, and anM₅-drain. The latch 118, 122 can have a sixth transistor, M₆. M₆ canhave an M₆-source, an M₆-gate, and an M₆-drain. The latch 118, 122 canhave a seventh transistor, M₇. M₇ can have an M₇-source, an M₇-gate, andan M₇-drain. The latch 118, 122 can have an eighth transistor, M₈. M₈can have an M₈-source, an M₈-gate, and an M₈-drain. The latch 118, 122can have a ninth transistor, M₉. M₉ can have an M₉-source, an M₉-gate,and an M₉-drain. The latch 118, 122 can have a tenth transistor, M₁₀.M₁₀ can have an M₁₀-source, an M₁₀-gate, and an M₁₀-drain. Any one orcombination of the transistors of the slave latch 118 can be a metaloxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

In at least one embodiment, M₁, M₂, M₃, M₄, M₉, and M₁₀ are MOSFETs. Inat least one embodiment, M₅, M₆, M₇, and M₈ are FeFETs 102. M₁-drain canbe connected to data input D. M₁-gate can be connected to CLK. M₁-sourcecan be connected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain,M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₂-drain can beconnected to data input DN. M₂-gate can be connected to M₁-gate.M₂-source can be connected to M₅-gate, M₃-gate, M₁-source, M₇-gate,M₉-gate, M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₃-drain canbe connected to V_(DD). M₃-gate can be connected to M₅-gate, M₁-source,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₃-source can be connected to M₅-drain. M₄-drain can beconnected to V_(DD). M₄-gate can be connected to M₅-gate, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₁-source, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₄-source can be connected to M₆-drain. M₅-drain can beconnected to M₃-source. M₅-gate can be connected to M₁-source, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₅-source can be connected to M₅-gate, M₃-gate, M₂-source,M₇-gate, M₉-gate, M₁-source, M₆-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₆-drain canbe connected to M₄-source. M₆-gate can be connected to M₅-gate, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₁-source, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁₀-gate. M₆-source can be connected to M₅-gate, M₃-gate, M₂-source,M₇-gate, M₉-gate, M₅-source, M₁-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₇-drain canbe connected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate, M₁-source,M₈-drain, data output QN, M₈-gate, and M₁₀-gate. M₇-gate can beconnected to M₅-gate, M₃-gate, M₂-source, M₁-source, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁₀-gate. M₇-source can be connected toM₉-drain. M₁₀-drain can be connected to M₈-source. M₁₀-gate can beconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁-source. M₁₀-source can be connected to GND.

In terms of the physical layout design, the overhead of the FeFETs 102in embodiments of the latches of FIGS. 29, 30, 38, and 39 can bemitigated by properly sharing the drain and source active region withoutthe need for adding additional contacts for the drain and sourceterminals of the FeFETs 102.

FIG. 40 illustrates the operating mechanism of the latch topology ofFIG. 30 during sampling, showing charging and discharging routes. FIG.41 illustrates the operating mechanism of the latch topology of FIG. 30in a hold phase, showing charging and discharging routes. FIGS. 40-41illustrate the operation theory of an embodiment of the latch topologyof FIG. 30. During the sampling phase (high CLK), M₃ and M_(5b) form aninverter that can provide a fast settling output of QN and nopseudo-floating status. The always-on CMOS switch consisting of M₉ andM₁₀ delivers QN to drive the second inverter to provide Q. The feedbackloop of the switch is turned OFF to prevent racing short current duringthis sampling phase, and will be turned on to form a stable closed loopduring the hold phase (low CLK), as shown in FIG. 41. The restoreoperation is similar to the latch topology of FIG. 29, by sensing adifferent Q or QN to ground resistance and continuing to settle down toV_(DD) or GND in the feedback loop.

FIG. 42 shows the transient simulation waveforms of the latch topologyof FIG. 30. Along with the normal sampling and hold operations with astable V_(DD), it also shows successful backup and restore operations ofQ=‘0’ and Q=‘1’ during the power outages around 5 μs and 10 μs,respectively.

FIGS. 43-44 summarize the simulated energy vs CLK-to-Q delay performanceof embodiments of the latch with ×1 and ×4 driving capabilities atdifferent supply voltages, in comparison with the conventional CMOSvolatile latches. Simulations were carried out with 1.0 fF capacitorload, and an input rise and fall time of 20 ps for the input clock, D,and DN. Energy consumption included clocking and D/DN driving. Whilebeing aware that embodiments of the latches could operate at higherfrequencies, in this section of evaluation, all polarization switchingwas fully completed, and the energy in FIGS. 43-44 includes the energyfor Q/QN setup and also polarization switching as a backup operation. Asthe supply voltage reduces, simulation results summarized in FIGS. 43-44show that the energy per switching reduces and the delay increases.Embodiments of the latches have about 64% and 39% extra energy-delayproduct (EDP) over the CMOS latch. If there is no need for a completepolarization switching (in cases with a high data rate), it consumesless energy for each switching event.

FIGS. 45-48 show the energy and time for backup and restore operationsfor embodiments of the latch. As supply voltage increases, backup andrestore time decreases, and backup and restore energy increases. Beingan intrinsic nonvolatile latch, simulation results in FIGS. 45-48 alsoshow that the latches are very fast and energy-efficient for backup andrestore operations. For example, under 0.8V V_(DD), the backup time islower than 1.0 ns, and the intrinsic restore time is lower than 75 nsfor both each embodiment of the latch. It is noted that the intrinsicrestore time is obtained with an assumption of very fast supply voltagerecovery in a few ps. In real scenarios the supply voltage recoversslower (usually much larger than ns) and the capability of fastintrinsic restore operation guarantees that the overall restoreoperation closely follow the supply recovery. The restore energy isobtained based on 0.8 μs supply voltage ramp-up time to mimic realscenarios. Meanwhile, the backup and restore energy is lower than 3.0 fJfor the entire operating range of 0.5V to 1.0V. This can enableextremely low-energy backup and restore operations of the entireprocessor being carried out autonomously and in parallel withoutworrying about the peak current.

In some embodiments an improved DFF 120 can be generated by replacingany one or combination of its master latch and slave latch with anembodiment of the latch 118, 122 disclosed herein. FIG. 49 shows anembodiment of a DFF 120 with its slave latch 118 replaced with anembodiment of the latch topology of FIG. 29. The same topology of thelatch in FIG. 29 can be used but with a first slave transmission gate,S_(GATE1), in place of M₁ and a second transmission gate, S_(GATE2), inplace of M₂. For example, the output of S_(GATE1) can be connected toM₃-gate, M₃-source, M₄-source, M₄-gate, data output Q, S_(GATE2) output,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate. The output of S_(GATE2) can be connected to M₃-gate, M₃-source,M₄-source, M₄-gate, data output Q, S_(GATE1) output, M₅-gate, M₇-gate,M₅-drain, data output QN, M₆-drain, M₆-gate, and M₈-gate.

The master latch 122 can be connected to the slave latch 118 viaS_(GATE1) and S_(GATE2). For example, the master latch 122 can have afirst master transmission gate M_(GATE1), a first master inverter,M_(INV1), a second master inverter, M_(INV2), and a second mastertransmission gate, M_(GATE2). The input of M_(GATE1) can be connected toa data input signal, D. The output of M_(GATE1) can be connected to theinput of M_(INV1) and the input of S_(GATE1). The input of M_(INV1) canbe connected to the output of M_(GATE1). The output of M_(INV1) can beconnected to the input of M_(INV2) and the input of S_(GATE2). The inputof M_(INV2) can be connected to the output of M_(INV1). The output ofM_(INV2) can be connected to the input of M_(GATE2). The input ofM_(GATE2) can be connected to the output of M_(INV2). The output ofM_(GATE2) can be connected to the input of M_(GATE1) and the output ofM_(INV1). From this topology, the master latch 122 and slave latch 118can be connected with switches.

FIG. 50 shows another embodiment of a DFF 120 with its slave latch 122replaced with an embodiment of the latch topology of FIG. 29. The sametopology of the latch in FIG. 29 can be used but with a first slaveinverter, S_(INV1), in place of M₁ and a second slave inverter,S_(INV2), in place of M₂. For example, the output of S_(INV1) can beconnected to M₃-gate, M₃-source, M₄-source, M₄-gate, data output Q,S_(INV2) output, M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain,M₆-gate, and M₈-gate. The output of S_(INV2) can be connected toM₃-gate, M₃-source, M₄-source, M₄-gate, data output Q, S_(INV1) output,M₅-gate, M₇-gate, M₅-drain, data output QN, M₆-drain, M₆-gate, andM₈-gate.

The master latch 122 can be connected to the slave latch 118 viaS_(INV1) and S_(INV2). For example, the master latch 122 can have afirst master transmission gate M_(GATE1), a first master inverter,M_(INV1), a second master inverter, M_(INV2), and a second mastertransmission gate, M_(GATE2). The input of M_(GATE1) can be connected toa data input signal, D. The output of M_(GATE1) can be connected to theinput of M_(INV1) and the input of S_(INV1). The input of M_(INV1) canbe connected to the output of M_(GATE1). The output of M_(INV1) can beconnected to the input of M_(INV2) and the input of S_(INV2). The inputof M_(INV2) can be connected to the output of M_(INV1). The output ofM_(INV2) can be connected to the input of M_(GATE2). The input ofM_(GATE2) can be connected to the output of M_(INV2). The output ofM_(GATE2) can be connected to the input of M_(GATE1) and the output ofM_(INV1). From this topology, the master latch 122 and slave latch 118can be connected with clocked inverters for isolation.

FIG. 51 shows another embodiment of a DFF 120 with its slave latch 122replaced with an embodiment of the latch topology of FIG. 30 The sametopology of the latch in FIG. 30 can be used but with a slave inverter,S_(INV), in place of M₁ and M₂. For example, the output of S_(INV) canbe connected to M₃-gate, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source,M₃-source, M₉-source, M₁₀-source, M₅-drain, and M_(5b)-drain.

The master latch 122 can be connected to the slave latch 118 viaS_(INV). For example, the master latch 122 can have a first masterinverter M_(INV1), a second master inverter, M_(INV2), a third masterinverter, M_(INV3), and a master transmission gate, M_(GATE). The inputof M_(INV1) can be connected to a data input signal, D. The output ofM_(INV1) can be connected to the input of M_(INV2). The input ofM_(INV2) can be connected to the output of M_(INV1). The output ofM_(INV2) can be connected to the input of M_(INV3) and the input ofS_(INV). The input of M_(INV3) can be connected to the output ofM_(INV2). The output of M_(INV3) can be connected to the input ofM_(GATE). The input of M_(GATE) can be connected to the output ofM_(INV3). The output of M_(GATE) can be connected to the input ofM_(INV2) and the output of M_(INV1).

With reference to FIGS. 49-52, embodiments of the DFF 120 can beconfigured as a positive-edge-triggered DFF, wherein making the slavelatch 118 nonvolatile can simplify clocking during restore, as the slavelatch 118 is isolated from the input data when CLK is low (i.e., inhold/restore phase). With the topology of FIG. 49, the structure issimple and has the minimum overhead in terms of number of additionaltransistors (as compared to the conventional topology of FIG. 52).However, the driving strength of the master latch 122 should besufficient to make sure a new state could be set up in time for theslave latch 118. Also, the possible bleeding current from D through aninput switch would affect the timing behavior. FIG. 50 uses clockedinverters as a buffer to drive the slave latch 118 and to isolate thepossible bleeding current between master and slave stages. With thedesigns in FIGS. 51 and 52, clocked inverters instead of CMOS switchesare used to drive the master latch and slave latch to provide betterkick-back isolation between the two stages and the driver of D. It isnoted, however, that the DFF 120 of FIG. 51 has only 6 more transistorsthan the conventional CMOS DFF of FIG. 52, with a total of 30transistors including a local clock driver.

The setup and hold time of the DFF 120 with the topology in FIG. 51 willbe almost identical to that of the conventional CMOS volatile DFF inFIG. 52. This property can stem from a master latch of the samestructure and size being used in both designs that features a clockedinverter to provide isolation.

FIG. 53 shows the transient simulation waveforms of an embodiment of theDFF 120. With a steady V_(DD), embodiments of the DFF 120 can carry outthe positive-edge-triggered sample-and-hold operations. The intrinsicnon-volatility of latch topologies disclosed herein is inherited to theDFF 120. As shown in FIG. 53, during power failures, the polarization ofthe FeFETs 102 maintains stable. When power supply recovers, the restoreoperations automatically restore the output Q and QN to its previousstate before the power failure. In FIG. 53, the backup and restoreoperations for bit ‘0’ and bit ‘1’ are shown around 4-6 μs and 9-11 μs,respectively.

FIGS. 54-57 compare the backup and restore performance metrics of anembodiment of the DFF with a conventional DFF design based onferroelectric capacitor and another conventional DFF design based on aNCFET DFF. FIG. 54 shows supply voltage as a function of backup energyfor an embodiment of a DFF 120 compared to conventional DFFs. FIG. 55shows supply voltage as a function of restore energy for an embodimentof a DFF 120 compared to conventional DFFs. FIG. 56 shows supply voltageas a function of backup time for an embodiment of a DFF 120 compared toconventional DFFs. FIG. 57 shows supply voltage as a function of restoretime f for an embodiment of a DFF 120 compared to conventional DFFs.Conventional designs used more complex backup and restore circuitschemes, need multiple steps to carry out the operations, may causestatic leakage current if the polarization state is positive(low-resistance state). Some conventional DFF designs can causes tens oftimes higher energy overheads. Conversely, embodiments of the DFF 120 asignificant amount of energy could be saved for backup and restoreoperations, which can be due to the removal of the complex driving andsensing schemes for the ferroelectric capacitor. Thanks to the deeplyembedded logic-in-memory operation in the disclosed simple and effectivecircuit structure, embodiments of the DFF 120 facilitate low-energyoperations.

It is also noted that embodiments of the DFF 120 has lower backup andrestore speed than conventional DFFs. This can be due to the adoption oflow-power (high V_(TH)) CMOS transistors to achieve low leakage currentfor low-power IoT applications. For example, conventional NCFET basedDFFs have around 0.12 μW static leakage power when operating at 0.8Vsupply, while the embodiments of the DF 120 can have less than 0.2 nW at0.8V. The backup and restore speed of embodiments of the DFF 120 aresufficiently fast for most if not all scenarios, as charging anddischarging the supply network on the chip following a power failure andrecovery usually takes much longer time than a few nanoseconds. Theadoption of high V_(TH) MOSFETs in the main signal routes can alsoimprove the reliability during backup and restore operations.

FIG. 58 compares the energy versus delay between embodiments of the DFF120 and conventional DFF designs. Embodiments of the DFF 120 have around35% energy-delay-product overhead. Note that the energy here includesthe backup energy consumed after Q/QN settles down. For applicationswith a higher bit-rate or dynamic frequency scaling (DFS) in which theclock cycle is shorter than the polarization switching time, the energyoverhead could be much smaller. More importantly, for many IoTapplications in which the processor is normally idle, most energy isconsumed by the stand-by leakage. In these scenarios, a moderate energyoverhead is fairly acceptable.

Additional advantages of embodiments of the DFF 120 over someconventional DFF devices can stem from the fact that the conventionalDFF devices may be two-terminal devices, wherein the change of theirmemory state requires a static current or voltage across them for acertain period of time. Such static current, especially considering thewidened time window for write operations due to the impact of devicevariations, significant amount of energy will be consumed by them.Furthermore, the great scalability, low-voltage operation, high ON-OFFratio, and the unique external-control-free feature, highlightadditional advantage of embodiments of the DFF 120.

Given an FEFET 102 structure and the ferroelectric material, the tunableFeFET design parameter is the ferroelectric layer thickness T. Duringdevice optimizations, the first concern is the retention time. For FeFETmemory devices, it depends on the energy barrier between the twopolarization states. Increasing T_(FE) can helps increasing the coercivevoltage that is required to change the polarization. However, it resultsin a larger minimum required supply voltage, which indicates more energyconsumption each time the polarization is switched.

It is noted that the restore functionality of the embodiments of thelatches 118, 122 and DFFs 120 depends on the difference of the sensedresistance from Q/QN to GND or V_(DD), which indicates that thesensitivity of the sensed resistance may be critical for yield. Forsimplicity, only the sensed resistance to GND, i.e. RQ2GND, wasanalyzed. For en embodiment of the DFF 120, the sensed resistance can bedefined as the sum of the series FeFET drain-source resistance RFeFETand the NMOS drain-source resistance RCMOS. When storing a differentlatch bit information, the key difference in the initial sensedresistance, without considering process non-idealities, varies inRFeFET. As a result, the ratio of RQ2GND between the two branches in thelatch can be:

$\begin{matrix}{\Gamma = {R_{{Q\; 2\;{GND}},\;{\text{'}\text{1}\text{'}}}/R_{Q\; 2{GND}\text{'0'}}}} \\{= {\left( {R_{{NCFET},\;\text{'1'}} + R_{{CMOS},\;\text{'1'}}} \right)/\left( {R_{{NCFET},\;\text{'0'}} + R_{{CMOS},\text{'0'}}} \right)}} \\{\approx {R_{{CMOS},\;\text{'1'}}/{\left( {R_{{NCFET},\;\text{'0'}} + R_{{CMOS},\text{'0'}}} \right).}}}\end{matrix}$

A smaller Γ will lead to more stable restore operation and is morenoise-resistant. A small RCMOS or a large RFeFET, ‘0’ is thus helpful.Considering the orders of difference in the ON-OFF resistance of RFeFET,the approximation in the equation above is rather safe. For thispurpose, T_(FE) is set to be 8 nm so as to provide large ON-OFF stateresistance while enabling low-voltage operation. Since the degradationof F can be easily caused by the variation of the NMOS initialresistance, RCMOS, ‘0’ and RCMOS, ‘1’, analysis should be carried out.This is especially important for designs of the DFF 120, because anotherparallel branch (see M_(5b) and M_(6b)) is affecting F, too. Thedifference in RCMOS, ‘0’ and RCMOS, ‘1’ mainly comes from device sizemismatch and threshold voltage V_(TH) variation ΔV_(TH). By manuallyadding an opposite in-series gate driving voltage to the gate, as shownin FIG. 59, the impact of ΔV_(TH) can be quantified through a series ofsimulations. The results are summarized in FIG. 60, with V_(DD) ramp-uptime equal to 0.8 μs to mimic typical real scenarios. The results showthat, within the 0.5V to 1.0V supply voltage range, the design isreliable with ΔV_(TH) no more than 30 mV. Note that this result providesa fairly large margin for design, as all the MOSFETs in FIG. 59 arehaving an unfavorable direction of V_(TH) variation if the FeFETs on theleft and right branches store a negative and positive polarizationstate, respectively.

It is also interesting to find out, that the variation impact isindependent on the supply voltage within the given range of 0.5V to1.0V. This is because of the relatively long rising time for the supplyvoltage to recover, and the fact that the initial restore trend isalmost equal for scenarios with different V_(DD). To provide a small F,the latch is designed in a way that all CMOS transistors have a higherV_(TH) than the bottom two transistors connecting to FeFETs (e.g., M₇and M₈). By doing this, the following goals could be achieved: (i) Theresistance of M₇ and M_(5b), or that of M₈ and M_(th), plays a lesssignificant role than that of FeFETs, as M₇ is in series with the FeFET,and M_(5b) is in parallel with the FeFET. This will help built thecorrect rising trend of Q and QN when V_(DD) starts to recover. (ii)Static leakage current of the latch will not increase. This can beguaranteed by a proper FeFET design with a high OFF-state resistance.Given a certain ferroelectric material and transistor structure, thisOFF-state resistance could be tuned by varying T_(FE) and the width ofFeFET 102. The large inherent ON-OFF resistance ratio will help toreduce the impact of FeFET variation.

Embodiments of the DFF 120 could be strongly complementary to existingpower-gating approaches in both low and high-performance systems. Inaggressive, high speed systems using fine-grained, low-latencypower-gating techniques, the ability to power-gate stateful units up toand including entire processor cores within a handful of cycles wouldboth expand the scope of what can be power-gated and simplify designconstraints. While the impact of no need for backup and restore controlfor power-gating is still not yet fully explored, it is promising toopen up new possibilities for further energy savings and architectureoptimizations due to the reduced control complexity. On theenergy-harvesting end of the spectrum, one apparent benefit is thereduced backup and restore energy consumption and latency, whichimproves the utilization of harvested energy for the purposecomputation. The intrinsic non-volatility ensures no missing backupwithout the need for backup control, leading to prevention of roll-backoperations in the computation progress. While there are already works onnonvolatile processor optimizations, further architecture-leveloptimizations would be useful to capture the intrinsic non-volatility ofFeFET flip-flops. Meanwhile, it has been shown that the recovery time inNVPs after a power emergency are sometimes dominated by the recovery ofanalog components, such as ensuring PLL stability. While this limits theimpact of the rapid recovery time that NC-DFFs have in such systems,their rapid, completely distributed and low energy backup properties mayallow power gating of data path and other digital components fast enoughto divert energy during shorter or less severe power emergencies inorder to preserve analog functionality, using embodiments of the DFF120F cycle-latency (at NVP frequencies) power gating potential to shavemicroseconds off recovery times.

Embodiments of the NMV device 100 can be configured as a memory cell124. Embodiments of the memory cell 124 can be configured with a2-transistor FeFET 102 topology between the Wordline and the Readline(2T-memory cell 124) or a 3-transistor FeFET 102 topology between theWordline and Readline (3T-memory cell 124). Embodiments of the memorycell 124 can facilitate an improved memory access method.

For example, embodiments of the memory cell 124 can include at least oneFeFET 102 to provide intrinsic non-volatility, compatibility withcommercial CMOS processes, both high ON-state current and low OFF-statecurrent, and/or merged logic-memory functionality, which can facilitateconvenient writing and nondestructive reading for the memory cell 124.Embodiments of the memory cell 124 can have high energy-efficiency andhigh write speed, along with improved performance and energy versuslatency tradeoffs for writes. Embodiments of the memory cell 124 cansupport voltage-mode sensing for read access, which can broaden designspace flexibility in support of different application scenarios.

As noted herein, nonvolatile memory arrays can be used to reduce oreliminate static leakage power in embedded memories by completelyshutting down the power supply while retaining the stored data andcomputation progress. Conventional nonvolatile devices can be limited byrequiring the write operation to depend on the voltage change at theFeFET gate only and not concurrently at the FeFET drain and source. Thiscan require a doubled gate driving voltage range to set the memorystate, resulting in multi-supply overheads and loss of energyefficiency. In addition, a voltage-mode read is not supported withconventional topologies for nonvolatile devices, causing high designoverheads for read access in some scenarios due to bit-line currentsensing and voltage clamping.

FIGS. 61-63 show a FeFET 102 in a fin structure, which can be a MOSFETwith an extra ferroelectric gate insulator, such as doped hafniumdioxide. FIG. 61 shows a schematic for an N-type FeFET 102, FIG. 62shows a fin-structured FeFET device, and FIG. 63 shows a typicalhysteretic G_(DS)−V_(GS) extracted form one fin of a fin-structuredFeFET device at V_(DS)=10 mV. FeFET device parameters for the LKequation were: α=−1.05×109 m/F, β=1×107 m5/F/C2, and γ=6×1011 m9/F/C4.The ferroelectric material was adopted in this structure for the purposeof steep switching behavior with a sub-threshold swing (SS) lower than60 mV/dec so that the transistor could be used to build lower-powerlogic gates. Making use of the voltage booting function of the negativecapacitance of the ferroelectric material can be done to increase theinternal MOSFET gate voltage. In addition, as noted herein, increasingthe ferroelectric layer thickness (T_(FE)), when the negativeferroelectric capacitance is smaller than the positive MOSFET gatecapacitance, a hysteresis appears and may exhibit distinct ON and OFFstates with zero gate-source voltage (V_(GS)) based on the direction ofthe ferroelectric material polarization.

For conventional logic gates, hysteresis should be strictly controlledor minimized to comply with the logic operation. On the contrary, it isintriguing to use the hysteresis for low-power NVM applications.

FIG. 64 shows an exemplary energy landscape plot for an embodiment of aFeFET 102. FIG. 65 shows static internal states with an embodiment ofthe FeFET 102 biased at V_(GS)=0. The polarization state of theferroelectric material is stable at zero V_(GS). As the energy landscapeplot in FIG. 64 shows, the stable polarization state stays close to thetwo lowest-energy region. For a zero-V_(GS) FeFET in the OFF (or ON)state, a stable positive (or negative) voltage across the ferroelectriclayer, V_(FE), and accordingly a negative (or positive) internalgate-source voltage of the internal MOSFET, V_(MOS), lead to differentG_(DS) states.

The two nonvolatile G_(DS) states in FIG. 65 show over four orders ofdifference in magnitude, leading to low-cost sensing schemes todistinguish the state difference. This is superior to existingnonvolatile devices. The sharp transitioning between different statesalso helps to maintain a larger noise margin. These advantages come fromFeFET 102 features of: (i) the settling-down transition behavior in theenergy landscape as a passive amplification for V_(MOS), and (ii) thegain of the internal MOSFET from V_(MOS) to sensed current I_(DS). Forconventional nonvolatile devices. no MOSFET gain is intrinsicallyprovided and sensing the ferroelectric material is more complex andsensitive to the external bit-line parasitic capacitance.

With proper MOSFET work function engineering and ferroelectric materialdesign that matches the MOSFET properties, e.g. the gate capacitance, itis possible to locate the FeFET I-V hysteresis window around zero V_(GS)with embodiments of the FeFET 102. By tuning T_(FE), the hysteresiswidth could also be optimized to work under a proper supply voltage, asshown in FIG. 63.

Embodiments of the FeFET 102 can have integrated the NVM storage and thelogic transistor operating as a memory state amplifying reader. Suchintegration not only provides the opportunity to design a simplifiedlow-power sensing scheme, but also opens up new space for futurememory-oriented computing.

The polarization switching can be accomplished by applying a positive ornegative voltage across the ferroelectric layer 114. Different from thestate change in resistive memory devices, no static DC current isconsumed for embodiments of the FeFET 102 (biased with V_(DS)=0V).Furthermore, when considering the resistive memory device variations ofrequired write pulse duration, even more energy could be saved.

It should be noted that the ferroelectric material in FeFETs could bethe same as that in ferroelectric random access memory (FeRAM) devices,leading to similar memory features of retention time, endurance, etc.Yet, the FeFET memory read operation is non-destructive, whichoutperforms FeRAM. In addition, FeFET is fundamentally superior to FeRAMwith better distinguishability and access interface.

Referring to FIG. 66, embodiments of the 2T-memory cell 124 can includea first transistor T₁, a second transistor T₂, a bit line, BL, a firstWordline, WLW, and a second Wordline, WLR. T₁ can be a MOSFET. T₁ canhave a T₁-source, a T₁-gate, and a T₁-drain. T₂ can be a FeFET 102. T₂can have a T₂-source, a T₂-gate, and a T₂-drain. WLW can be configuredto receive and/or transmit a write signal for write operations. WLR canbe configured to receive and/or transmit a read signal for readoperations. T₂-drain can be connected to BL and WLW. T₂-gate can beconnected to WLW. T₂-source can be connected to T₁-drain. T₁-gate can beconnected to WLR and BL. T₁-source can be connected to GND.

Some embodiments can include a plurality of 2T-memory cells 124. Forexample, a memory cell array 126 can include a first 2T-memory cell 124,a second 2T-memory cell 124, a third 2T-memory cell 124, etc. In atleast one embodiment, the memory cell array 126 can include a first2T-memory cell 124, a second 2T-memory cell 124, a third 2T-memory cell124, a fourth 2T-memory cell 124, a fifth 2T-memory cell 124, a sixth2T-memory cell 124, a seventh 2T-memory cell 124, and an eighth2T-memory cell 124. The memory cell array 126 can have a first BL, BL1,a second BL, BL2, a third BL, BL3, and a fourth BL, BL4. The memory cellarray 126 can have a first WLW, WLW1, a second WLW, WLW2, a first WLR,WLR1, and a second WLR, WLR2. Each memory cell 124 can have a T₁ and aT₂, wherein T₁ is a MOSFET and T₂ is a FeEFT 102. For example, the first2T-memory cell 124 can have a first T₁ and a first T₂. The second2T-memory cell 124 can have a second T₁ and a second T₂. The third2T-memory cell 124 can have a third T₁ and a third T₂. The fourth2T-memory cell 124 can have a fourth T₁ and a fourth T₂. The fifth2T-memory cell 124 can have a fifth T₁ and a fifth T₂. The sixth2T-memory cell 124 can have a sixth T₁ and a sixth T₂. The seventh2T-memory cell 124 can have a seventh T₁ and a seventh T₂. The eighth2T-memory cell 124 can have an eighth T₁ and a eighth T₂. Each of WLW1and WLW2 can be configured to receive and/or transmit a write signal forwrite operations. Each of WLR1 and WLR2 can be configured to receiveand/or transmit a read signal for read operations.

For the first 2T-memory cell 124, first cell T₂-drain can be connectedto BL1 and WLW1. First cell T₂-gate can be connected to WLW1. First cellT₂-source can be connected to first cell T₁-drain. First cell T₁-gatecan be connected to WLR1 and BL1. First cell T₁-source can be connectedto GND. For the second 2T-memory cell 124, second cell T₂-drain can beconnected to BL2 and WLW1. Second cell T₂-gate can be connected to WLW1.Second cell T₂-source can be connected to second cell T₁-drain. Secondcell T₁-gate can be connected to WLR1 and BL2. Second cell T₁-source canbe connected to GND. For the third 2T-memory cell 124, third cellT₂-drain can be connected to BL3 and WLW1. Third cell T₂-gate can beconnected to WLW1. Third cell T₂-source can be connected to third cellT₁-drain. Third cell T₁-gate can be connected to WLR1 and BL3. Thirdcell T₁-source can be connected to GND. For the fourth 2T-memory cell124, fourth cell T₂-drain can be connected to BL4 and WLW1. Fourth cellT₂-gate can be connected to WLW1. Fourth cell T₂-source can be connectedto fourth cell T₁-drain. Fourth cell T₁-gate can be connected to WLR1and BL4. Fourth cell T₁-source can be connected to GND. For the fifth2T-memory cell 124, fifth cell T₂-drain can be connected to BL1 andWLW2. Fifth cell T₂-gate can be connected to WLW2. Fifth cell T₂-sourcecan be connected to fifth cell T₁-drain. Fifth cell T₁-gate can beconnected to WLR2 and BL1. Fifth cell T₁-source can be connected to GND.For the sixth 2T-memory cell 124, sixth cell T₂-drain can be connectedto BL2 and WLW2. Sixth cell T₂-gate can be connected to WLW2. Sixth cellT₂-source can be connected to sixth cell T₁-drain. Sixth cell T₁-gatecan be connected to WLR2 and BL2. Sixth cell T₁-source can be connectedto GND. For the seventh 2T-memory cell 124, seventh cell T₂-drain can beconnected to BL3 and WLW2. Seventh cell T₂-gate can be connected toWLW2. Seventh cell T₂-source can be connected to seventh cell T₁-drain.Seventh cell T₁-gate can be connected to WLR2 and BL3. Seventh cellT₁-source can be connected to GND. For the eighth 2T-memory cell 124,eighth cell T₂-drain can be connected to BL4 and WLW2. Eighth cellT₂-gate can be connected to WLW2. Eighth cell T₂-source can be connectedto eighth cell T₁-drain. Eighth cell T₁-gate can be connected to WLR2and BL4. Eighth cell T₁-source can be connected to GND.

FIG. 67 shows the operating status of the 2T-memory cell 124 of FIG. 66in terms of G_(DS) versus VG_(S). In the power-off mode, the bit lineand word lines are grounded and the FeFETs 102 stay with G_(DS) beinghigh or low as illustrated in the power-OFF mode. With the power turnedon, the cells in rows not being read or written are in the idle modewith WLW voltage set to about V_(DD)/2 and WLR to GND. Thus, thisidle-mode cell does not deliver a DC current or affect the BL sensingresult. Note that V_(BL) could vary from GND to V_(DD) as BL could becontrolled by other active rows being read or written. In this case, theFeFET 102 operating point could be in a consecutive region (as opposedto single pinpoints) in the G_(DS) versus V_(GS) curve. To prevent theidle-mode FeFET polarization state being flipped, the stable hysteresisregion should safely cover this range through device-circuit co-designmethods like tuning T.

Embodiments of the memory cell array 126 can operate with a row-wiseread. FIG. 68 shows an exemplary read operation with pre-charged BL.V_(WLW) is set to about V_(DD)/2 to keep the FeFET polarizationunchanged. V_(WLR) is set to V_(DD) to turn on T₁. The memory cell array126 topology supports both voltage-sensing and current-sensing read. Ina voltage-sensing read, BL can be pre-charged, to V_(DD) or some othervoltage above GND. When WLR is enabled to turn on T₁, V_(BL) may remainhigh if T₂ is in the OFF state, or discharge quickly to GND if T₂ is inthe ON state. Such a difference in BL settling behavior could beconveniently sensed with a voltage sense amplifier connecting to BL. Inaddition, the memory read result may be achieved before BL eventuallysettles down to GND, as long as the sense amplifier could effectivelytell the voltage difference of V_(BL) between the two memory readscenarios.

If current-sensing read is adopted, the bit line voltage V_(BL) shouldbe fixed, and the current from the bit line to the ground through thecell in the selected row can be sensed by a current sense amplifier,similar to existing resistive memory array sensing schemes. This canhelp to reduce the sensing latency by avoiding charging and dischargingthe long bit-line parasitic capacitance for a large-size array. Thecapability of supporting both sensing modes provides more case-to-casedesign flexibility.

FIG. 69 shows an exemplary write operation setup. V_(BL) can be set toGND and V_(DD) to write ‘0’ and ‘1’, respectively. V_(WLR) can be set toGND to turn off T₁. V_(WLW) can be set to V_(DD) in the first phase andthen GND in the second phase. As WLW is shared with all bits in theword, such a two-phase write method enables writing different values fordifferent bits in the same word line. To write ‘0’, the FeFETpolarization switching to the desired positive state occurs during thefirst phase with V_(WLW)=V_(DD). Setting V_(WLW) to be beyond thehysteresis rising edge (with T₂ source voltage at GND) triggers thepolarization switching. To write ‘1’, the FeFET polarization switchingoccurs for the desired negative state. If the polarization state of theT₂ is positive, the internal node X would charge to V_(DD) by BL throughthe ON-state of T₂. Then, when V_(WLW) becomes GND in the second phase,T₂ is biased with V_(G)=GND, V_(S)=V_(D)=V_(DD), leading to apolarization switching to be negative. It is noted that, V_(WLW) couldalso be set to GND and V_(DD) in the first and second write phases,respectively.

FIG. 70 is a snapshot of a SPICE transient simulation waveform of anembodiment of the memory cell array 126, showing polarization statusesfor the FeFET transistors. For the simulation, T_(FE) is 8 nm. ρ was0.25 and V_(DD) was 0.6V. The polarization switching speed in FIG. 70was based on a relatively large ρ and consequently a slow FeFET. Theswitching speed could be much faster with a smaller ρ. The read latencyin FIG. 70 depends on the bit line parasitic capacitance, whichincreases as the array size increases.

Embodiments of a 3T-memory cell 124 can provide additional designflexibility in certain scenarios. FIG. 71 shows an embodiment of a3T-memory cell 124, with the 3T-memory cell 124 in a two-bit linetopology and a single-bit line topology for a voltage-sensing read mode.

The 3T-memory cell 124 having a two-bit line topology can have a firsttransistor, T₁, a second transistor, T₂, a third transistor T₃, a firstbit line, BLW, a second bit line, BLR, a WLW, a WLR, and aWordline-Readline, WLRL. T₁ and T₃ can be MOSFETs. T₂ can be a FeFET102. T₁ can have a T₁-source, a T₁-gate, and a T₁-drain. T₂ can have aT₂-source, a T₂-gate, and a T₂-drain. T₃ can have a T₃-source, aT₃-gate, and a T₃-drain. T₁-drain can be connected to T₂-gate. T₁-gatecan be connected to WLW. T₁-source can be connected to BLW. T₂-drain canbe connected to T₃-source. T₂-gate can be connected to T₁-drain.T₂-source can be connected to WLRW. T₃-drain can be connected to BLR.T₃-gate can be connected to WLR. T₃-source can be connected to T₂-drain.Any one or combination of BLW, WLW, and WLRW can be connected to GND.WLR can be connected to V_(DD).

The 3T-memory cell 124 can have one write-access N-type MOS transistorT₁ controlled by the write-access word line WLW, one read-access N-typeMOS transistor T₃ controlled by the read-access word line WLR, and tostorage N-type FeFET T₂ connecting to the wordline WLRW for both readand write. The cell 124 uses two bit lines: BLR for read and BLW forwrite. In power-OFF and idle modes, all word lines and bit lines couldbe safely grounded. Both voltage sensing and current sensing could beused to perform read. In the voltage-sensing read, T₃ can be turned ON,and WLRW set to GND. The pre-charged V_(BLR) will remain almostunchanged with an OFF-state T₂ or drop quickly to GND with an ON-stateT₂. A voltage thresholding of V_(BLR) could provide the sensing resultfor a voltage-mode sensing scheme. In the current-mode sensing scheme,V_(BLR) can be fixed and T₃ turned ON. Thus, the current delivered bythe cell can be sensed at the bit line, providing another meaningfuloption for energy-delay optimization in a larger memory array.

The 3T-memory cell 124 having a single-bit line topology can have afirst transistor, T₁, a second transistor, T₂, a third transistor T₃, abit line, BL, a WLW, a WLR, and a WLRL. T₁ and T₃ can be MOSFETs. T₂ canbe a FeFET 102. T₁ can have a T₁-source, a T₁-gate, and a T₁-drain. T₂can have a T₂-source, a T₂-gate, and a T₂-drain. T₃ can have aT₃-source, a T₃-gate, and a T₃-drain. T₁-drain can be connected toT₂-gate. T₁-gate can be connected to WLW. T₁-source can be connected toBL. T₂-drain can be connected to T₃-drain. T₂-gate can be connected toT₁-drain. T₂-source can be connected to WLRW. T₃-drain can be connectedto T₂-drain. T₃-gate can be connected to WLR. T₃-source can be connectedto BL.

FIG. 72 shows an embodiment of a 3T-memory cell 124 having a two-bitline topology in write mode using a two-step write method. A row-wisewrite operation is shown when T₃ is turned OFF, T₁ is turned ON, BLW setto GND, and V_(DD) to write ‘1’ and write ‘0’. A two-phase voltagesetting for WLRW can be adopted, changing from V_(DD) to GND. Writeoperation for ‘1’ and ‘0’ occurs in the V_(DD) phase with V_(GS)=−V_(DD)and GND phase with V_(GS)=V_(DD), respectively. If the two bit lines aremerged into one to form the single-bit line topology, bit line BL wouldinherit the BLW setting of the two-bit line topology. V_(WLRW) could beGND in the first phase and V_(DD) in the second phase for the write.

FIG. 73 shows SPICE transient simulation waveforms for an embodiment ofthe cell 124. For the simulation, T_(FE) was 10 nm, ρ was 0.1, andV_(DD) was 0.8V. Voltage-sensing mode read was applied. An optionalwrite pre-charge of write bit line BLW was adopted so that V_(BLW) wasset slightly prior to the setting of word lines. In practice, this wouldimprove the write latency as the polarization switching in the writeoperation can start as soon as the word line is ready. In thesimulations, a 50 fF parasitic capacitor was assumed for each bit, a 10nm FeFET model was used, based on the LK equation with PZT as theferroelectric material.

For fair comparison, no negative supply was used. For the conventionalcell designs, the use of negative supply voltage of −V_(DD) wasprevented by equally shifting up all supply and biasing voltages byV_(DD), as shown in FIG. 74. Different from embodiments of the memorycell 124 disclosed herein, conventional cell designs have the same andfixed drain and source voltage during writing ‘0’ and ‘1’, resulting inthe need of a doubled voltage range, as illustrated in FIG. 74. Notethat this supply voltage range is 2×V_(DD) even if the negative supplyis kept in the conventional cell design. Embodiments of the memory cell124 were also evaluated with T_(FE)=12 nm for a wider FeFET hysteresiswindow to extend the supply voltage operation range.

The write energy is the average energy consumed to write ‘1’ and ‘0’from a different prior state. The write operation latency covers adifferent period of time between the embodiments of the memory cell 124and conventional cell designs. For embodiments of the For the memorycell 124 that adopt two-phase write, it is the sum of latency in writing‘0’ and ‘1’. For the conventional cell designs, the write operationlatency is defined as the maximum latency to write ‘0’ and write ‘1’.

FIG. 75 shows the simulated write energy per cell versus the writelatency for embodiments of the memory cell, as compared to aconventional memory cell. In addition to low write energy and latency ofthe disclosed designs, a few observations are manifest: First, a highersupply voltage leads to less latency and more energy consumption. Due tono-DC-current write, no more than 2% of the average write energy isconsumed to switch the polarization. Second, the 2T-memory cell 124 witha higher T_(FE) of 12 nm has higher write latency than that 2T-memorycell 124 with 10.5 nm T_(FE), even under the same supply voltage. Thisis because of a different ferroelectric energy landscape and widerhysteresis width. Third, the 3T-memory cell 124 with 10.5 nm T_(FE) hasthe write energy-latency curve that lies in between the two curvesegments of the 2T-memory cell 124. At the higher-voltage segment, the3T-memory cell 124 has lower latency than the 2T-memory cell 124 withT_(FE)=12 nm, mainly because of an intrinsically faster FeFET. At thelower-voltage segment, the 3T-memory cell 124 has higher write latencythan the 2T-memory cell 124 with T_(FE)=10.5 nm, mainly because of thewrite mechanism differences: before WLW is effectively triggered, the2T-memory cell 124 can use a prior read operation and BL preset to setthe desired voltage for both drain and source of the FeFET. While the3T-memory cell 124 has neither the source nor drain of the FeFET preset(after a read operation, the internal node X is desired to be GND butcharged to V_(DD), and is desired to be V_(DD) but was discharged toGND). Last, conventional cells have the highest write energy. This ismainly because of the required doubled voltage to charge the bit line.In addition, it also results in higher voltage stress on thewrite-access transistor, which may induce a stability problem and also apower problem as the drain-body or source-body interface diode may beturned on with a high voltage across it.

It should be noted that, the write latency was based on ρ set as 0.1.The energy and latency as a function of ρ are provided in FIG. 76,wherein the left side plot if for a fixed ρ and the right side plot isfor a varying ρ at V_(DD)=07.5V. The write energy is almost constant andunrelated to the polarization switching speed, while the write latencystrongly linearly reacts to the kinetic coefficient, as is expected.

The current-sensing read performance was not simulated as it stronglydepends on the current sense amplifier design. Therefore, only thevoltage-sensing read operations were evaluated. The read operationenergy is the average energy consumed to read ‘1’ and ‘0’. As reading‘1’ does not noticeably change the bit line voltage, the read operationlatency is actually equal to the latency for the read of ‘0’, which isdefined as the delay from the effective word line triggering point (with50% voltage change) to the point when the read bit line voltage hasreduced by 150 mV. Practically, a voltage difference of 150 mV could besensed with a voltage-mode amplifier that does not require a high gain.

FIG. 77 shows the simulated read energy per cell versus read latency foran embodiment of the memory cell 124. Data for a conventional memorycell was is not included as it does not support voltage-mode sensing.Thanks to the ultra-low OFF-state current and high ON-state current,ultra-low read energy and latency are achieved for embodiments of thememory cell 124. In addition, the following conclusions could bereached: First, most read energy is consumed in pre-charging the bitline capacitance. For read, pre-charging the bit line is required forboth ‘0’ and ‘1’. In contrast, for write, pre-charging of the bit lineis required only for writing ‘1’ in the 2T and 3T topologies.Consequently, more energy is consumed by read than write. Second, theread latency reduces as the supply voltage increases. This is becausethe read access transistors have lower resistance and discharge the bitline faster. For the 2T topology with different T_(FE), the read latencydifference is not quite significant at 0.7V and 0.8V because thedischarging current is mainly limited by the read access MOSFET and theFeFET is not the bottleneck element. Third, the 2T topology hasrelatively lower read latency than the 3T topology. This is because (i)the 2T topology is biased at V_(DD)/2 at the FeFET gate while the 3Ttopology is biased with GND at the FeFET gate; (ii) the 2Ttoplogy alwayshas V_(GS)=V_(DD) for the access NMOS while the 3T topology hasV_(GS)=V_(DD) only at the beginning point for the read access transistorT₃. It is also feasible to use a lower voltage to pre-charge the bitline for read to reduce the read energy consumption as long as thesensing scheme is not the bottleneck.

Table 4 summarizes the benchmarking results, where the comparison ofembodiment so of the memory cell's 124 access performance, density,peripheral circuitry requirement is displayed. It is also interesting toconsider the OFF-to-Ready energy, which is the energy needed to wake upa cell array 126 from completely OFF state to the idle state ready forread and write. With the 2T topology, considering some idle-statebiasing voltage settings are non-zero, the memory controller has toraise its voltage level accordingly and thus consumes extra energy.Embodiments of the 3T topology can operate with the largest supplyvoltage range, and does not require an extra supply voltage of V_(DD)/2or 2×V_(DD), making it a good fit in scenarios when multi-supply is notavailable.

TABLE 4 Comparison of a Conventional Memory Cell and Embodiments of TheDisclosed Memory Cells 124 Specifications Conv. Cell 2T-Topology3T-Topology Number of transistors 2 2 3 Low voltage operation No Yes YesWrite energy Medium Low Low Write speed^(&) Medium High HighCurrent-mode read speed^(#) High High High Current-mode read energy^(#)Low Low Low Voltage-mode read speed — High High Voltage-mode read energy— Low Low OFF-to-Ready energy High Medium Low Additional supply voltage2VDD Approx. ½ VDD Not Needed ^(&)Write speed is compared based on thesimilar write energy consumption; ^(#)Current-mode read speed and energyare roughly evaluated based on the amount of sensed current in the OFFstate and the ON state

Embodiments of the NVM device 100 can be configured as a 4T-topology(4T) B&R circuitry 116. For example, the B&R circuitry 116 can includeonly four transistors. This can be done to reduce area overhead. Someembodiments can include an improved DFF 120 by incorporating anembodiment of the 4T B&R circuitry 116. With embodiments of the 4T B&Rcircuitry 116, the transistor number of B&R circuitry is lowered, andthe backup control can be embedded into the supply voltage modulationwith lowered routing cost. The energy-delay product overhead in thenormal-mode operation can be below 5%. Embodiments of the DFF 120 withsuch a 4T B&R circuitry 116 can provide area- and energy-efficientnonvolatile computing for power-gating and energy-harvestingapplications.

Power gating for idle digital circuits is an effective low-power designapproach to reducing the leakage power by shutting down the supply. Thiscan be a useful for both portable and server processors whose designoptimizations often get tangled up with the battery life and the thermallimit, respectively. In practice, power-gated DFF states need to besaved in nonvolatile memories.

One key optimization for DFF backup and restore operations can be tofocus on lowering the consumed energy. Another key optimization for DFFscan be to reduce the area overhead. This can have a significant impactin modern processors where complex pipelining logic and sometimes largeregister cache files are already adopted based on many flip-flops.Embodiments of the 4T B&R circuitry 116 and/or DFF 120 have a reducedthe area overhead. In addition, the backup control is embedded into thesupply voltage modulation, which reduces the routing cost since there isno need for an extra backup control signal.

While FeFETs can be designed hysteresis-free in I_(D)−V_(G) to complywith the conventional logic gate switching style, embodiments of the B&Rcircuitry 116 and/or the DFF 120 can utilize the FeFET 102characteristics of I_(D)−V_(G) hysteresis. FIG. 78 shows typical 10 nmn-type FeFET G_(DS)−V_(G) curves with over 5 orders of magnitudes in thesensed drain-source channel conductions (G_(DS)) between the bistableON/OFF nonvolatile states sensed at zero V_(G). Applying V_(GS) beyondthe hysteresis edge triggers polarization switching. To ensure asufficient energy barrier in the hysteresis window for desired noiseimmunity and retention time, the ferroelectric layer 114 thickness(T_(FE)) must be carefully tuned. As disclosed herein, this T_(FE)determines the supply voltage needed in backup operations.

FIG. 79 shows an embodiment of the 4T B&R circuitry 116. The 4T B&Rcircuit 116 can have a first transistor, M₁. M₁ can have an M₁-source,an M₁-gate, and an M₁-drain. The 4T B&R circuit 116 can have a secondtransistor, M₂. M₂ can have an M₂-source, an M₂-gate, and an M₂-drain.The 4T B&R circuit 116 can have a third transistor, M₃. M₃ can have anM₃-source, an M₃-gate, and an M₃-drain. The 4T B&R circuit 116 can havea fourth transistor, M₄. M₄ can have an M₄-source, an M₄-gate, and anM₄-drain. Any one or combination of the transistors of the 4T B&Rcircuit 116 can be a metal oxide semiconductor field effect transistor(MOSFET) or a FeFET 102.

The 4T B&R circuit 116 can further include a first branch 101 and asecond branch 103. The first branch 101 can include M₁, M₃, and GND. Thesecond branch 103 can include M₂, M₄, and GND. Depending on the inputs,either the first branch 101 or the second branch 103 operates as abackup branch or a restore branch. For example, when the first branch101 operates as a backup branch, the second branch 103 operates as arestore branch. When the first branch 101 operates as a restore branch,the second branch 103 operates as a backup branch. Particular noteshould be made to the cross-coupled circuit connection between M₃ andthe second branch 103 and M₄ and the first branch 101.

In some embodiments, the B&R circuit 116 can be connected to a slavelatch 118. (See FIG. 80). Can be done to generate a DFF 120. Forexample, the first branch 101 and the second branch 103 can be connectedto a slave latch 118 to form a DFF 120.

In at least one embodiment, M₁ and M₂ are MOSFETs. In at least oneembodiment, M₃ and M₄ are FeFETs 102. M₁-drain can be connected toM₃-source. M₁-gate can be connected to a restore signal input signal andM₂-gate. M₁-source can be connected to GND. M₂-drain can be connected toM₄-source. M₂-gate can be connected to M₁-gate. M₃-drain can beconfigured to be connected to a slave latch 118, which can be via thefirst branch 101. M₃-drain can be connected to M₄-gate, M₄-drain,M₃-gate, and to the second branch 103. M₃-gate can be connected toM₄-gate, M₄-drain, M₃-drain, and to the second branch 103. M₃-source canbe connected to M₁-drain. M₄-drain can be configured to be connected tothe slave latch 118, which can be via the second branch 103. M₄-draincan be connected to M₃-gate, M₃-drain, M₄-gate, and to the first branch103. M₄-gate can be connected to M₃-gate, M₃-drain, M₄-drain, and to thefirst branch 103. M₄-source can be connected to M₂-drain.

Referring to FIG. 80, in at least one embodiment, the 4T B&R circuit 116can be configured as a B&R circuit 116 that may be used to form anembodiment of a DFF 120. In some embodiments an improved DFF 120 can begenerated by replacing any one or combination of B&R circuit with anembodiment of the 4T B&R circuit 116 disclosed herein. FIG. 80 shows anembodiment of a DFF 120 having a master latch 122 and a slave latch 118similar to the ones disclosed in FIG. 6 and a 4T B&R circuit 116.

The master latch 122 can have a first master inverter M_(INV1), a secondmaster inverter, M_(INV2), a third master inverter, M_(INV3), and amaster transmission gate, M_(GATE). The input of M_(INV1) can beconnected to a data input signal, D. The output of M_(INV1) can beconnected to the input of M_(INV2). The input of M_(INV2) can beconnected to the output of M_(INV1). The output of M_(INV2) can beconnected to the input of M_(INV3). The input of M_(INV3) can beconnected to the output of M_(INV2). The output of M_(INV3) can beconnected to the input of M_(GATE). The input of M_(GATE) can beconnected to the output of M_(INV3). The output of M_(GATE) can beconnected to the input of M_(INV2) and the output of M_(INV1).

The slave latch 118 can have a first slave inverter, S_(INV1), a secondslave inverter, S_(INV2), a third slave inverter, S_(INV3), and a slavetransmission gate, S_(GATE). The input of S_(INV1) can be connected tothe output of M_(INV2). The input of S_(INV2) can be connected to theoutput of S_(INV1). The output of S_(INV2) can be connected to the inputof S_(INV3) and to a data output Q. The input of S_(INV3) can beconnected to the output of S_(INV2). The output of S_(INV3) can beconnected to the input of S_(GATE). The output of S_(GATE) can beconnected to the input of S_(INV2) and the output of S_(INV1).

A clock driver, CLK can be used to generate an in-phase clock signal, c,and opposite-phase clock signal, cn, for M_(INV1), M_(GATE), S_(INV1),and/or S_(GATE). Embodiments of the CLK can include a first clockinverter, CLK_(INV1), having an output connected to an input of a secondclock inverter, CLK_(INV2). CLK_(INV1) can be configured to generate cn.CLK_(INV2) can be configured to generate c. Each of M_(GATE) andS_(GATE) can be a gate circuit for transmitting or blocking the outputsignal from the master latch 122 or slave latch 118, respectively, inresponse to the clock signal from CLK.

M₃-drain can be connected to the output of S_(GATE), the output ofS_(INV1), and the input of S_(INV2). For example, the first branch 101can be connected to the output of S_(GATE), the output of S_(INV1), andthe input of S_(INV2). M₄-drain can be connected to the input ofS_(INV3), the output of S_(INV2), and data output Q. For example, thesecond branch 103 can be connected to the input of S_(INV3), the outputof S_(INV2), and data output Q.

In some embodiments, in the OFF mode, the voltage supply and all inputscan be grounded, and the FeFETs 102 (M₃ and M₄) stay stable with eitherpositive or negative polarization. In the NORMAL mode, the restore canbe grounded and the two N-type MOS transistors T₁ and T₂ can be turnedOFF, so the DFF 120 operates like a conventional DFF. The normal-modesupply voltage can be adjusted dynamically for the best trade-offbetween C-to-Q delay and energy. The FeFET device parameters, includingT_(FE), however, a may not be adjustable for a different hysteresiswindow width after fabrication. Therefore, in the normal-mode, thesupply voltage can be designed to stay safely within the FeFEThysteresis window to avoid unnecessary FeFET polarization switching. Inthe backup mode, the restore input remains grounded, and the supplyvoltage is raised beyond the FeFET hysteresis edge, enablingpolarization switching if a different DFF state was saved in the FeFETs102 (M₃ and M₄). FIG. 81 shows an embodiment of the DFF 120 in a backupoperation, with the DFF 120 state Q being high in voltage as an example.For M₃, a high gate-source voltage provides sufficient positive voltageacross the ferroelectric layer, ensuring that M₃ stays at or switches tothe positive polarization state. For M₄, an opposite voltage across thegate and source makes it enter or stay at the negative polarizationstate. Note that M₁ and M₂ are turned OFF, so the initial charge atnodes X and Y does not affect the final polarization states. After thepolarization settles, the DFF state is saved, and the supply could besafely turned off for power saving, or remain high as needed if standbyor continuous computation is preferred.

FIG. 82 shows an embodiment of the DFF 120 in a restore operation. Inthe restore mode, the clock input C remains low to isolate the slavelatch 118 from the master latch 122, and the restore control signalstays high to turn on both M₁ and M₂ before the supply ramps up. Asshown in FIG. 82, the branch with positive FeFET polarization clamps QNto ground tightly but detaches Q from the ground. As the supplyrecovers, the latching structure in the slave latch 118 further enhancessuch a trend and finally leads to full settling-down.

Once T_(FE) is fixed, the DFF 120 has the minimum required V_(DD) tocarry out successful polarization switching in the backup mode, and themaximum V_(DD) to avoid polarization switching in the normal mode. Thesetwo V_(DD) levels are similar in magnitude due to the steep switchinghysteresis edges.

Conventional DFF devices need four extra transistors to isolate the B&Rcircuitry and the slave latch, so the supply voltage in the normal modecan be higher, as compared to embodiments of the DFF 120 disclosedherein. For fair comparison, the same FeFETs were used in both anembodiment of the DFF 120 and a conventional DFF to conduct an analysis.Therefore, when the normal-mode supply voltage is lower than that in thebackup mode, both the conventional DFF and embodiments of the DFF 120raise the supply voltage accordingly for backups. As will be shown,embodiments of the DFF 120 can re-use the supply voltage modulation unitwithout introducing other overheads.

FIG. 83 shows an example of transient simulation waveform snapshots, inwhich all operation modes are shown. FIGS. 84-87 show performanceevaluations for embodiments of the DFF 120. FIG. 84 shows V_(DD) v.backup time for embodiments of the DFF 120. FIG. 85 shows V_(DD) v.backup energy for embodiments of the DFF 120. FIG. 86 shows V_(DD) v.restore energy for embodiments of the DFF 120. FIG. 87 shows clock to Qenergy v. clock to Q delay for embodiments of the DFF 120. The intrinsicDFF restore time is lower than 100 ps for all design process corners.Thus, the actual DFF restore time is practically almost the same as thesupply voltage recovery time due to the relatively large capacitive loadin the supply network. The restore energy has very little dependence onT_(FE), as almost all energy is consumed to charge the capacitance ateach internal node and a restore operation does not trigger polarizationswitching. For backup performance, scenarios when the polarization statewas flipped were considered. Two observations are noted: (i) when alarger T_(FE) is adopted, the wider ferroelectric hysteresis window andhigher energy barrier lead to more switching time and energy for thebackup operation; (ii) while reducing the normal-mode supply voltage iswidely used for lower C-to-Q sample-and-hold energy in the normal mode,it also leads to more backup time and energy due to more supply voltageincrease to reach the backup mode supply voltage level.

FIG. 88 summarizes the backup time versus backup energy for the secondobservation, wherein a comparison of the performance of backup time andenergy between an embodiment of the DFF 120 conventional DFF devices ismade. While both designs have ultra-fast backup speed in ns andultra-low backup energy in fJ, some differences are observed. Theconventional DFF design with a fixed T_(FE) has a relatively flat backuptime because its backup operation starts with the supply voltage raisedto the same level when the dedicated backup control signal is triggered.In comparison, the backup operation is faster in the inventive DFF 120due to direct contact between the slave latch and the FeFETs without anyisolation transistors used in the conventional DFF design.

FIG. 89 further provides detailed energy-delay product (EDP) overheadfor en embodiment of the DFF 120, in comparison with the conventionalDFF devices. While the inventive DFF 120 pays slightly higher EDP formuch lower area overhead (˜50%), this EDP overhead is no more than 5%for both designs. Table 5 summarizes the comparisons of metrics of anembodiment of the DFF 120 with conventional DFF devices.

TABLE 5 Metric Comparisons of an Embodiment of the DFF 120 withConventional DFF Devices Conventional Conventional Embodiment of the DFFDFF DFF 120 Number of B&R 2 or 4 8 4 transistors Normal-mode EDP 30%-50%<5% <5% overhead External B&R control Not needed Not needed Neededsignals Backup and restore: fj, ns fj, ns fj, ns energy, speed Immunityto variation Medium High High and noise * Restore signal needed; Backupcontrol is embedded into the supply signal.

Embodiments of the DFF 120 can reduce the area overhead of DFF by ˜50%,through harnessing the feature of logic-memory fusion in FeFETs.Embodiments of the DFF 120 consumes only ˜fJ energy to accomplish thenonvolatile backup and restore operations within ns, with anenergy-delay performance overhead below 5%.

It should be understood that modifications to the embodiments disclosedherein can be made to meet a particular set of design criteria. Forinstance, the number of or configuration of MOSFETs, FeFETs 102, DFFs120, slave latches 118, master latches 122, memory cells 124, eyepieces108, and/or other components or parameters may be used to meet aparticular objective. In addition, any of the embodiments of the NVMdevices 100 (e.g., B&R circuit 116, 4T B&R circuit 116, clave latch 118,master latch 122, DFF 120, memory cell 124, etc.) disclosed herein canbe connected to other embodiments of the NVM devices 100 (e.g., B&Rcircuit 116, 4T B&R circuit 116, clave latch 118, master latch 122, DFF120, memory cell 124, etc.) to generate a device.

It will be apparent to those skilled in the art that numerousmodifications and variations of the described examples and embodimentsare possible in light of the above teachings of the disclosure. Thedisclosed examples and embodiments are presented for purposes ofillustration only. Other alternative embodiments may include some or allof the features of the various embodiments disclosed herein. Forinstance, it is contemplated that a particular feature described, eitherindividually or as part of an embodiment, can be combined with otherindividually described features, or parts of other embodiments. Theelements and acts of the various embodiments described herein cantherefore be combined to provide further embodiments.

Therefore, it is the intent to cover all such modifications andalternative embodiments as may come within the true scope of thisinvention, which is to be given the full breadth thereof. Additionally,the disclosure of a range of values is a disclosure of every numericalvalue within that range, including the end points. Thus, while certainexemplary embodiments of apparatuses and methods of making and using thesame have been discussed and illustrated herein, it is to be distinctlyunderstood that the invention is not limited thereto but may beotherwise variously embodied and practiced within the scope of thefollowing claims.

It should also be appreciated that some components, features, and/orconfigurations may be described in connection with only one particularembodiment, but these same components, features, and/or configurationscan be applied or used with many other embodiments and should beconsidered applicable to the other embodiments, unless stated otherwiseor unless such a component, feature, and/or configuration is technicallyimpossible to use with the other embodiment. Thus, the components,features, and/or configurations of the various embodiments can becombined together in any manner and such combinations are expresslycontemplated and disclosed by this statement. Thus, while certainexemplary embodiments of the NVM devices 100 have been shown anddescribed above, it is to be distinctly understood that the invention isnot limited thereto but may be otherwise variously embodied andpracticed within the scope of the following claims.

We claim:
 1. A nonvolatile memory (NVM) device, comprising a circuittopology having at least one Fe field effect transistor (FeFET)configured to exhibit a wide current-voltage (I-V) hysteresis coveringzero gate bias, wherein: the circuit topology is configured as a backupand restore circuit (B&R circuit); the B&R circuit comprising: a firsttransistor, M₁, M₁ having an M₁-source, an M₁-gate, and an M₁-drain; asecond transistor, M₂, M₂ having an M₂-source, an M₂-gate, and anM₂-drain; a third transistor, M₃, M₃ having an M₃-source, an M₃-gate,and an M₃-drain; a fourth transistor, M₄, M₄ having an M₄-source, anM₄-gate, and an M₄-drain; a fifth transistor, M₅, M₅ having anM₅-source, an M₅-gate, and an M₅-drain; a sixth transistor, M₆, M₆having an M₆-source, an M₆-gate, and an M₆-drain; a seventh transistor,M₇, M₇ having an M₇-source, an M₇-gate, and an M₇-drain; an eighthtransistor, M₈, M₈ having an M₈-source, an M₈-gate, and an M₈-drain; afirst branch and a second branch, the first branch including M₁, M₂, M₅,M₇, and a ground, GND, the second branch including M₃, M₄, M₆, and M₈;each of M₁, M₂, M₃, M₄, M₇, and M₈ is a metal-oxide-semiconductorfield-effect transistor (MOSFET) and each of M₅ and M₆ is a FeFET;M₁-gate being connected to a backup control signal input, B_(kp_input)and M₃-gate; M₁-drain being connected to M₂-drain; M₁-drain beingconfigured to be connected to a slave latch via the first branch;M₁-source being connected to M₅-source and M₇-drain; M₂-drain beingconnected to M₁-drain; M₂-drain being configured to be connected to theslave latch via the first branch; M₂-gate being connected to a backupand restore control signal input, B_(kp)+R_(str) and M₃-gate; M₂-sourcebeing connected to M₆-gate, M₅-drain, M₅-gate, M₆-drain, and M₃-source;M₃-drain being connected to M₄-drain; M₃-drain being configured to beconnected to the slave latch via the second branch; M₃-gate beingconnected to B_(kp)+R_(str) and M₁-gate; M₃-source being connected toM₅-gate, M₆-drain, M₅-drain, M₂-source, and M₆-gate; M₄-drain beingconnected to M₃-drain; M₄-drain being configured to be connected to theslave latch via the second branch; M₄-gate being connected to a backupcontrol signal output, B_(kp_output); M₄-source being connected toM₆-source and M₈-drain; M₅-drain being connected to M₂-source, M₅-gate,M₆-gate, M₆-drain, and M₃-source; M₅-gate being connected to M₃-source,M₆-drain, M₆-gate, M₂-source, and M₅-drain; M₅-source being connected toM₇-drain and M₁-source; M₆-drain being connected to M₃-source, M₅-gate,M₆-gate, M₅-drain, and M₂-source; M₆-gate being connected to M₂-source,M₅-drain, M₅-gate, M₆-drain, and M₃-source; M₆-source being connected toM₄-source and M₈-drain; M₇-drain being connected to M₁-source andM₅-source; M₇-gate being connected to a restore input control signal,R_(str); M₇-source being connected to GND via the first branch; M₈-drainbeing connected to M₄-source and M₆-source; M₈-gate being connected toM₇-gate; and M₈-source being connected to GND via the second branch. 2.A nonvolatile memory (NVM) device, comprising a circuit topology havingat least one Fe field effect transistor (FeFET) configured to exhibit awide current-voltage (I-V) hysteresis covering zero gate bias, wherein:the circuit topology is configured as a D-Flip Flop (DFF); the DFFcomprising a master latch, a slave latch, and a backup and restorecircuit (B&R circuit); the master latch comprising: a first masterinverter M_(INV1), a second master inverter, M_(INV2), a third masterinverter, M_(INV3), and a master transmission gate, M_(GATE); input ofM_(INV1) being connected to a data input signal, D; output of M_(INV1)being connected to input of M_(INV2), input of M_(INV2) being connectedto output of M_(INV1), output of M_(INV2) being connected to input ofM_(INV3), input of M_(INV3) being connected to output of M_(INV2),output of M_(INV3) being connected to input of M_(GATE); input ofM_(GATE) being connected to output of M_(INV3); and output of M_(GATE)being connected to input of M_(INV2) and output of M_(INV1); the slavelatch comprising: a first slave inverter, S_(INV1), a second slaveinverter, S_(INV2), a third slave inverter, S_(INV3), and a slavetransmission gate, S_(GATE); input of S_(INV2) being connected to outputof M_(INV2); input of S_(INV2) being connected to output of S_(INV1);output of S_(INV2) being connected to input of S_(INV3) and to a dataoutput Q; input of S_(INV3) being connected to output of S_(INV2);output of S_(INV3) being connected to input of S_(GATE); and output ofS_(GATE) being connected to input of S_(INV2) and output of S_(INV1);and the B&R circuit comprising: a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain; a second transistor, M₂, M₂having an M₂-source, an M₂-gate, and an M₂-drain; a third transistor,M₃, M₃ having an M₃-source, an M₃-gate, and an M₃-drain; a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain; afifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, and anM₅-drain; a sixth transistor, M₆, M₆ having an M₆-source, an M₆-gate,and an M₆-drain; a seventh transistor, M₇, M₇ having an M₇-source, anM₇-gate, and an M₇-drain; an eighth transistor, M₈, M₈ having anM₈-source, an M₈-gate, and an M₈-drain; a first branch and a secondbranch, the first branch including M₁, M₂, M₅, M₇, and a ground, GND,the second branch including M₃, M₄, M₆, and M₈; each of M₁, M₂, M₃, M₄,M₇, and M₈ is a metal-oxide-semiconductor field-effect transistor(MOSFET) and each of M₅ and M₆ is a FeFET; M₁-gate is connected to abackup control signal input, B_(kp_input) and M₃-gate; M₁-drain isconnected to M₂-drain; M₁-drain is configured to be connected to theslave latch via the first branch; M₁-source is connected to M₅-sourceand M₇-drain; M₂-drain is connected to M₁-drain; M₂-drain is configuredto be connected to the slave latch via the first branch; M₂-gate isconnected to a backup and restore control signal input, B_(kp)+R_(str)and M₃-gate; M₂-source is connected to M₆-gate, M₅-drain, M₅-gate,M₆-drain, and M₃-source; M₃-drain is connected to M₄-drain; M₃-drain isconfigured to be connected to the slave latch via the second branch;M₃-gate is connected to B_(kp)+R_(str) and M₁-gate; M₃-source isconnected to M₅-gate, M₆-drain, M₅-drain, M₂-source, and M₆-gate;M₄-drain is connected to M₃-drain; M₄-drain is configured to beconnected to the slave latch via the second branch; M₄-gate is connectedto a backup control signal output, B_(kp_output); M₄-source is connectedto M₆-source and M₈-drain; M₅-drain is connected to M₂-source, M₅-gate,M₆-gate, M₆-drain, and M₃-source; M₅-gate is connected to M₃-source,M₆-drain, M₆-gate, M₂-source, and M₅-drain; M₅-source is connected toM₇-drain and M₁-source; M₆-drain is connected to M₃-source, M₅-gate,M₆-gate, M₅-drain, and M₂-source; M₆-gate is connected to M₂-source,M₅-drain, M₅-gate, M₆-drain, and M₃-source; M₆-source is connected toM₄-source and M₈-drain; M₇-drain is connected to M₁-source andM₅-source; M₇-gate is connected to a restore input control signal,R_(str); M₇-source is connected to GND via the first branch; M₈-drain isconnected to M₄-source and M₆-source; M₈-gate is connected to M₇-gate;and M₈-source is connected to GND via the second branch.
 3. Anonvolatile memory (NVM) device, comprising a circuit topology having atleast one Fe field effect transistor (FeFET) configured to exhibit awide current-voltage (I-V) hysteresis covering zero gate bias, wherein:the circuit topology is configured as a latch configured to have aninput D; the latch comprising: a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain; a second transistor, M₂, M₂having an M₂-source, an M₂-gate, and an M₂-drain; a third transistor,M₃, M₃ having an M₃-source, an M₃-gate, and an M₃-drain; a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain; afifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, and anM₅-drain; a sixth transistor, M₆, M₆ having an M₆-source, an M₆-gate,and an M₆-drain; a seventh transistor, M₇, M₇ having an M₇-source, anM₇-gate, and an M₇-drain; an eighth transistor, M₈, M₈ having anM₈-source, an M₈-gate, and an M₈-drain; a ninth transistor, M₉, M₉having an M₉-source, an M₉-gate, and an M₉-drain; a tenth transistor,M₁₀, M₁₀ having an M₁₀-source, an M₁₀-gate, and an M₁₀-drain; aneleventh transistor, M₁₁, M₁₁ having an M₁₁-source, an M₁₁-gate, and anM₁₁-drain; a twelfth transistor, M₁₂, M₁₂ having an M₁₂-source, anM₁₂-gate, and an M₁₂-drain; a thirteenth transistor, M_(5b), M_(5b)having an M_(5b)-source, an M_(5b)-gate, and an M_(5b)-drain; afourteenth transistor, M_(6b), M_(6b) having an M_(6b)-source, anM_(6b)-gate, and an M_(6b)-drain; each of M₁, M₂, M₃, M₄, M₇, M₈, M₉,M₁₀, and M₁₁ is a metal oxide semiconductor field effect transistor(MOSFET); each of M₅ and M₆ is a FeFET; M₁-drain being connected toM₂-drain and a data input D; M₁-gate being connected to a clock driver,CLK; M₁-source being connected to M₂-source, M₃-gate, M₅-gate, M₇-gate,M₁₁-source, M₁₂-source, M₃-source, M₉-source, M₁₀-source, M₅-drain, andM_(5b)-drain; M₂-drain being connected to M₁-drain and data input D;M₂-gate being connected to CLK; M₂-source being connected to M₁-source,M₃-gate, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain; M₃-drain being connected to avoltage supply, V_(DD); M₃-gate being connected to M₁-source, M₂-source,M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, M₅-drain, and M_(5b)-drain; M₃-source can be connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₁₂-source, M₃-gate,M₉-source, M₁₀-source, M₅-drain, and M_(5b)-drain; M₄-drain beingconnected to V_(DD); M₄-gate being connected to a data output QN, a dataoutput Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain,M₁₂-drain, M_(6b)-drain, and M₆-drain; M₄-source being connected to dataoutput QN, data output Q, M₆-gate, M₈-gate, M₄-gate, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain; M₅-drainbeing connected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M_(5b)-drain; M₅-gatebeing connected to M₁-source, M₂-source, M₅-drain, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, M_(5b)-gate, andM_(5b)-drain; M₅-source being connected to M₇-drain; M_(5b)-drain beingconnected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₁₀-source, and M₅-drain; M_(5b)-gatebeing connected to M₅-gate; M_(5b)-source being connected to ground,GND; M₆-drain being connected to data output QN, data output Q, M₆-gate,M₈-gate, M₄-source, M₉-drain, M₁₀-drain, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₄-gate; M₆-gate being connected to data output QN,data output Q, M₆-drain, M_(6b)-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₄-gate; M₆-sourcebeing connected to M₈-drain; M_(6b)-drain being connected to data outputQN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₁₀-drain,M₁₁-drain, M₁₂-drain, M₄-gate, and M₆-drain; M_(6b)-gate being connectedto M₆-gate; M_(6b)-source being connected to GND; M₇-drain beingconnected to M₅-source; M₇-gate being connected to M₁-source, M₂-source,M₅-gate, M₅-drain, M₁₁-source, M₁₂-source, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain; M₇-source being connected to GND; M₈-drainbeing connected to M₆-source; M₈-gate being connected to data output QN,data output Q, M₆-gate, M₄-gate, M₄-source, M₉-drain, M₁₀-drain,M₁₁-drain, M₁₂-drain, M_(6b)-drain, and M₆-drain, M₈-source can beconnected to GND; M₉-drain being connected to data output QN, dataoutput Q, M₆-gate, M₈-gate, M₄-source, M₄-gate, M₁₀-drain, M₁₁-drain,M₁₂-drain, M_(6b)-drain, and M₆-drain; M₉-gate being connected toV_(DD); M₉-source being connected to M₁-source, M₂-source, M₅-gate,M₇-gate, M₁₁-source, M₁₂-source, M₃-source, M₅-drain, M₁₀-source, andM_(5b)-drain; M₁₀-drain being connected to data output QN, data outputQ, M₆-gate, M₈-gate, M₄-source, M₉-drain, M₄-gate, M₁₁-drain, M₁₂-drain,M_(6b)-drain, and M₆-drain; M₁₀-gate being connected to GND; M₁₀-sourcebeing connected to M₁-source, M₂-source, M₅-gate, M₇-gate, M₁₁-source,M₁₂-source, M₃-source, M₉-source, M₅-drain, and M_(5b)-drain; M₁₁-drainbeing connected to data output QN, data output Q, M₆-gate, M₈-gate,M₄-source, M₉-drain, M₁₀-drain, M₄-gate, M₁₂-drain, M_(6b)-drain, andM₆-drain; M₁₁-gate being connected to CLK; M₁₁-source being connected toM₁-source, M₂-source, M₅-gate, M₇-gate, M₅-drain, M₁₂-source, M₃-source,M₉-source, M₁₀-source, and M_(5b)-drain; M₁₂-drain being connected todata output QN, data output Q, M₆-gate, M₈-gate, M₄-source, M₉-drain,M₁₀-drain, M₁₁-drain, M₄-gate, M_(6b)-drain, and M₆-drain; M₁₂-gatebeing connected to CLK; and M₁₂-source being connected to M₁-source,M₂-source, M₅-gate, M₇-gate, M₁₁-source, M₅-drain, M₃-source, M₉-source,M₁₀-source, and M_(5b)-drain.
 4. A nonvolatile memory (NVM) device,comprising a circuit topology having at least one Fe field effecttransistor (FeFET) configured to exhibit a wide current-voltage (I-V)hysteresis covering zero gate bias, wherein: the circuit topology isconfigured as a latch configured to have a differential-driving inputpair D/DN; the latch comprising: a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain; a second transistor, M₂, M₂having an M₂-source, an M₂-gate, and an M₂-drain; a third transistor,M₃, M₃ having an M₃-source, an M₃-gate, and an M₃-drain; a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain; afifth transistor, M₅, M₅ having an M₅-source, an M₅-gate, and anM₅-drain; a sixth transistor, M₆, M₆ having an M₆-source, an M₆-gate,and an M₆-drain; a seventh transistor, M₇, M₇ having an M₇-source, anM₇-gate, and an M₇-drain; an eighth transistor, M₈, M₈ having anM₈-source, an M₈-gate, and an M₈-drain; each of M₁, M₂, M₃, M₄, M₇, andM₈ is a metal oxide semiconductor field effect transistor (MOSFET); eachof M₅ and M₆ is a FeFET; M₁-drain being connected to a data input D;M₁-gate being connected to a clock driver, CLK; M₁-source beingconnected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain,a data output Q, a data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate; M₂-drain being connected to data input DN; M₂-gatebeing connected to M₁-gate; M₂-source being connected to M₅-gate,M₃-gate, M₅-source, M₁-source, M₇-gate, M₇-drain, a data output Q, adata output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate;M₃-drain being connected to a voltage supply, V_(DD); M₃-gate beingconnected to M₅-gate, M₁-source, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate; M₃-source being connected to M₅-drain; M₄-drainbeing connected to V_(DD); M₄-gate being connected to M₅-gate, M₃-gate,M₅-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₁-source; M₄-source beingconnected to M₆-drain; M₅-drain being connected to M₃-source; M₅-gatebeing connected to M₁-source, M₃-gate, M₅-source, M₂-source, M₇-gate,M₇-drain, data output Q, data output QN, M₆-source, M₈-drain, M₈-gate,M₆-gate, and M₄-gate; M₅-source being connected to M₅-gate, M₃-gate,M₁-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate; M₆-drain beingconnected to M₄-source; M₆-gate being connected to M₅-gate, M₃-gate,M₅-source, M₂-source, M₇-gate, M₇-drain, data output Q, data output QN,M₆-source, M₈-drain, M₈-gate, M₁-source, and M₄-gate; M₆-source beingconnected to M₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain,data output Q, data output QN, M₁-source, M₈-drain, M₈-gate, M₆-gate,and M₄-gate; M₇-drain being connected to M₅-gate, M₃-gate, M₅-source,M₂-source, M₇-gate, M₁-source, data output Q, data output QN, M₆-source,M₈-drain, M₈-gate, M₆-gate, and M₄-gate; M₇-gate being connected toM₅-gate, M₃-gate, M₅-source, M₂-source, M₁-source, M₇-drain, data outputQ, data output QN, M₆-source, M₈-drain, M₈-gate, M₆-gate, and M₄-gate;M₇-source being connected to ground, GND; M₈-drain being connected toM₅-gate, M₃-gate, M₅-source, M₂-source, M₇-gate, M₇-drain, data outputQ, data output QN, M₆-source, M₁-source, M₈-gate, M₆-gate, and M₄-gate;M₈-gate being connected to M₅-gate, M₃-gate, M₅-source, M₂-source,M₇-gate, M₇-drain, data output Q, data output QN, M₆-source, M₈-drain,M₁-source, M₆-gate, and M₄-gate; and M₈-source being connected to GND.5. A nonvolatile memory (NVM) device, comprising a circuit topologyhaving at least one Fe field effect transistor (FeFET) configured toexhibit a wide current-voltage (I-V) hysteresis covering zero gate bias,wherein: the circuit topology is configured as a latch configured tohave a differential-driving input pair D/DN; the latch comprising: afirst transistor, M₁, M₁ having an M₁-source, an M₁-gate, and anM₁-drain; a second transistor, M₂, M₂ having an M₂-source, an M₂-gate,and an M₂-drain; a third transistor, M₃, M₃ having an M₃-source, anM₃-gate, and an M₃-drain; a fourth transistor, M₄, M₄ having anM₄-source, an M₄-gate, and an M₄-drain; a fifth transistor, M₅, M₅having an M₅-source, an M₅-gate, and an M₅-drain; a sixth transistor,M₆, M₆ having an M₆-source, an M₆-gate, and an M₆-drain; a seventhtransistor, M₇, M₇ having an M₇-source, an M₇-gate, and an M₇-drain; aneighth transistor, M₈, M₈ having an M₈-source, an M₈-gate, and anM₈-drain; a ninth transistor, M₉, M₉ having an M₉-source, an M₉-gate,and an M₉-drain; a tenth transistor, M₁₀, M₁₀ having an M₁₀-source, anM₁₀-gate, and an M₁₀-drain; each of M₁, M₂, M₃, M₄, M₉, and M₁₀ is ametal oxide semiconductor field effect transistor (MOSFET); each of M₅,M₆, M₇, and M₈ is a FeFET; M₁-drain being connected to a data input D;M₁-gate being connected to a clock driver, CLK; M₁-source beingconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source,M₆-source, a data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, a dataoutput QN, M₈-gate, and M₁₀-gate; M₂-drain being connected to a datainput DN; M₂-gate being connected to M₁-gate; M₂-source being connectedto M₅-gate, M₃-gate, M₁-source, M₇-gate, M₉-gate, M₅-source, M₆-source,data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN,M₈-gate, and M₁₀-gate; M₃-drain being connected to a voltage supply,V_(DD); M₃-gate being connected to M₅-gate, M₁-source, M₂-source,M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate; M₃-sourcebeing connected to M₅-drain; M₄-drain being connected to V_(DD); M₄-gatebeing connected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₆-source, data output Q, M₆-gate, M₁-source, M₇-drain,M₈-drain, data output QN, M₈-gate, and M₁₀-gate; M₄-source beingconnected to M₆-drain; M₅-drain being connected to M₃-source; M₅-gate cbeing connected to M₁-source, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain,M₈-drain, data output QN, M₈-gate, and M₁₀-gate; M₅-source beingconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₁-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, dataoutput QN, M₈-gate, and M₁₀-gate; M₆-drain being connected to M₄-source;M₆-gate being connected to M₅-gate, M₃-gate, M₂-source, M₇-gate,M₉-gate, M₅-source, M₆-source, data output Q, M₁-source, M₄-gate,M₇-drain, M₈-drain, data output QN, M₈-gate, and M₁₀-gate; M₆-sourcebeing connected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate,M₅-source, M₁-source, data output Q, M₆-gate, M₄-gate, M₇-drain,M₈-drain, data output QN, M₈-gate, and M₁₀-gate; M₇-drain can beconnected to M₅-gate, M₃-gate, M₂-source, M₇-gate, M₉-gate, M₅-source,M₆-source, data output Q, M₆-gate, M₄-gate, M₁-source, M₈-drain, dataoutput QN, M₈-gate, and M₁₀-gate; M₇-gate can be connected to M₅-gate,M₃-gate, M₂-source, M₁-source, M₉-gate, M₅-source, M₆-source, dataoutput Q, M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate,and M₁₀-gate; M₇-source can be connected to M₉-drain; M₁₀-drain can beconnected to M₈-source; M₁₀-gate can be connected to M₅-gate, M₃-gate,M₂-source, M₇-gate, M₉-gate, M₅-source, M₆-source, data output Q,M₆-gate, M₄-gate, M₇-drain, M₈-drain, data output QN, M₈-gate, andM₁-source; and M₁₀-source can be connected to ground, GND.
 6. Anonvolatile memory (NVM) device, comprising a circuit topology having atleast one Fe field effect transistor (FeFET) configured to exhibit awide current-voltage (I-V) hysteresis covering zero gate bias, wherein:the circuit topology is configured as a plurality of 2-transistor (2T)memory cells arranged in a memory cell array cell; each 2T-memory cellcomprising: a first transistor T₁, a second transistor T₂, a bit line,BL, a first Wordline, WLW, and a second Wordline, WLR; T₁ being a metaloxide semiconductor field effect transistor (MOSFET) and T₂ being aFeFET; T₁ having a T₁-source, a T₁-gate, and a T₁-drain; T₂ having aT₂-source, a T₂-gate, and a T₂-drain; WLW being configured to receiveand/or transmit a write signal for write operations; WLR beingconfigured to receive and/or transmit a read signal for read operations;T₂-drain being connected to BL and WLW; T₂-gate being connected to WLW;T₂-source being connected to T₁-drain; T₁-gate being connected to WLRand BL; and T₁-source being connected to ground, GND; wherein the memorycell array comprises: a first 2T-memory cell, a second 2T-memory cell, athird 2T-memory cell, a fourth 2T-memory cell, a fifth 2T-memory cell, asixth 2T-memory cell, a seventh 2T-memory cell, and an eighth 2T-memorycell, each memory cell having a T₁ and a T₂, wherein T₁ is a MOSFET andT₂ is a FeEFT, wherein: the first 2T-memory cell has a first T₁ and afirst T₂; the second 2T-memory cell has a second T₁ and a second T₂; thethird 2T-memory cell has a third T₁ and a third T₂; the fourth 2T-memorycell has a fourth T₁ and a fourth T₂; the fifth 2T-memory cell has afifth T₁ and a fifth T₂; the sixth 2T-memory cell 124 has a sixth T₁ anda sixth T₂; the seventh 2T-memory cell has a seventh T₁ and a seventhT₂; the eighth 2T-memory cell 124 has an eighth T₁ and a eighth T₂; anda first BL, BL1, a second BL, BL2, a third BL, BL3, and a fourth BL,BL4; a first WLW, WLW1, a second WLW, WLW2, a first WLR, WLR1, and asecond WLR, WLR2, wherein each of WLW1 and WLW2 is configured to receiveand/or transmit a write signal for write operations, and each of WLR1and WLR2 is configured to receive and/or transmit a read signal for readoperations; the first cell T₂-drain being connected to BL1 and WLW1; thefirst cell T₂-gate being connected to WLW1; the first cell T₂-sourcebeing connected to first cell T₁-drain; the first cell T₁-gate beingconnected to WLR1 and BL1; the first cell T₁-source being connected toground, GND; the second cell T₂-drain being connected to BL2 and WLW1;the second cell T₂-gate being connected to WLW1; the second cellT₂-source being connected to second cell T₁-drain; the second cellT₁-gate being connected to WLR1 and BL2; the second cell T₁-source beingconnected to GND; the third cell T₂-drain being connected to BL3 andWLW1; the third cell T₂-gate being connected to WLW1; the third cellT₂-source being connected to third cell T₁-drain; the third cell T₁-gatebeing connected to WLR1 and BL3; the third cell T₁-source beingconnected to GND; the fourth cell T₂-drain being connected to BL4 andWLW1; the fourth cell T₂-gate being connected to WLW1; the fourth cellT₂-source being connected to fourth cell T₁-drain; the fourth cellT₁-gate being connected to WLR1 and BL4; the fourth cell T₁-source beingconnected to GND; the fifth cell T₂-drain being connected to BL1 andWLW2; the fifth cell T₂-gate being connected to WLW2; the fifth cellT₂-source being connected to fifth cell T₁-drain; the fifth cell T₁-gatebeing connected to WLR2 and BL1; the fifth cell T₁-source beingconnected to GND; the sixth cell T₂-drain being connected to BL2 andWLW2; the sixth cell T₂-gate being connected to WLW2; the sixth cellT₂-source being connected to sixth cell T₁-drain; the sixth cell T₁-gatebeing connected to WLR2 and BL2; the sixth cell T₁-source beingconnected to GND; the seventh cell T₂-drain being connected to BL3 andWLW2; the seventh cell T₂-gate being connected to WLW2; the seventh cellT₂-source being connected to seventh cell T₁-drain; the seventh cellT₁-gate being connected to WLR2 and BL3; the seventh cell T₁-sourcebeing connected to GND; the eighth cell T₂-drain being connected to BL4and WLW2; the eighth cell T₂-gate being connected to WLW2; the eighthcell T₂-source being connected to eighth cell T₁-drain; the eighth cellT₁-gate being connected to WLR2 and BL4; and the eighth cell T₁-sourcebeing connected to GND.
 7. A nonvolatile memory (NVM) device, comprisinga circuit topology having at least one Fe field effect transistor(FeFET) configured to exhibit a wide current-voltage (I-V) hysteresiscovering zero gate bias, wherein: the circuit topology is configured asa 3-transistor (3T) memory cell; the 3T-memory cell comprising: a firsttransistor, T₁, a second transistor, T₂, a third transistor T₃, a firstbit line, BLW, a second bit line, BLR, a Wordline Write, WLW, a WordlineRead, WLR, and a Wordline-Readline, WLRL; each of T₁ and T3 is a metaloxide semiconductor field effect transistor (MOSFET), and T₂ is a FeFET;T₁ has a T₁-source, a T₁-gate, and a T₁-drain; T₂ has a T₂-source, aT₂-gate, and a T₂-drain; T₃ has a T₃-source, a T₃-gate, and a T₃-drain;T₁-drain being connected to T₂-gate; T₁-gate being connected to WLW;T₁-source being connected to BLW; T₂-drain being connected to T₃-source;T₂-gate being connected to T₁-drain; T₂-source being connected to WLRW;T₃-drain being connected to BLR; T₃-gate being connected to WLR;T₃-source being connected to T₂-drain; at least one of BLW, WLW, andWLRW being connected to ground, GND; and WLR being connected to avoltage supply, V_(DD).
 8. A nonvolatile memory (NVM) device, comprisinga circuit topology having at least one Fe field effect transistor(FeFET) configured to exhibit a wide current-voltage (I-V) hysteresiscovering zero gate bias, wherein: the circuit topology is configured asa 3-transistor (3T) memory cell; the 3T-memory cell comprising: a firsttransistor, T₁, a second transistor, T₂, a third transistor T₃, a bitline, BL, a Wordline Write, WLW, a Wordline Read, WLR, and aWordline-Readline, WLRL; each of T₁ and T₃ is a metal oxidesemiconductor field effect transistor (MOSFET), and T₂ is a FeFET; T₁has a T₁-source, a T₁-gate, and a T₁-drain; T₂ has a T₂-source, aT₂-gate, and a T₂-drain; T₃ has a T₃-source, a T₃-gate, and a T₃-drain;T₁-drain being connected to T₂-gate; T₁-gate being connected to WLW;T₁-source being connected to BL; T₂-drain being connected to T₃-drain;T₂-gate being connected to T₁-drain; T₂-source being connected to WLRW;T₃-drain being connected to T₂-drain; T₃-gate being connected to WLR;and T₃-source being connected to BL.
 9. A nonvolatile memory (NVM)device, comprising a circuit topology having at least one Fe fieldeffect transistor (FeFET) configured to exhibit a wide current-voltage(I-V) hysteresis covering zero gate bias, wherein: the circuit topologyis configured as a backup and restore circuit (B&R circuit); the B&Rcircuit comprising: a first transistor, M₁, M₁ having an M₁-source, anM₁-gate, and an M₁-drain; a second transistor, M₂, M₂ having anM₂-source, an M₂-gate, and an M₂-drain; a third transistor, M₃, M₃having an M₃-source, an M₃-gate, and an M₃-drain; a fourth transistor,M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain; a first branchcomprising M₁, M₃, and ground, GND; a second branch comprising M₂, M₄,and GND; each of M₁ and M₂ is a metal oxide semiconductor field effecttransistor (MOSFET); each of M₃ and M₄ is a FeFET; M₁-drain beingconnected to M₃-source; M₁-gate being connected to a restore signalinput signal and M₂-gate; M₁-source being connected to GND; M₂-drainbeing connected to M₄-source; M₂-gate being connected to M₁-gate;M₃-drain configured to be connected to a slave latch via the firstbranch; M₃-drain being connected to M₄-gate, M₄-drain, M₃-gate, and tothe second branch; M₃-gate being connected to M₄-gate, M₄-drain,M₃-drain, and to the second branch; M₃-source being connected toM₁-drain; M₄-drain configured to be connected to the slave latch via thesecond branch; M₄-drain being connected to M₃-gate, M₃-drain, M₄-gate,and to the first branch; M₄-gate being connected to M₃-gate, M₃-drain,M₄-drain, and to the first branch; and M₄-source being connected toM₂-drain.
 10. A nonvolatile memory (NVM) device, comprising a circuittopology having at least one Fe field effect transistor (FeFET)configured to exhibit a wide current-voltage (I-V) hysteresis coveringzero gate bias, wherein: the circuit topology is configured as a D-FlipFlop (DFF); the DFF comprising a master latch, a slave latch, and abackup and restore circuit (B&R circuit); the master latch comprising: afirst master inverter M_(INV1), a second master inverter, M_(INV2), athird master inverter, M_(INV3), and a master transmission gate,M_(GATE); input of Mm being connected to a data input signal, D; outputof Mm being connected to input of M_(INV2); input of M_(INV2) beingconnected to output of M_(INV1); output of M_(INV2) being connected toinput of M_(INV3); input of M_(INV3) being connected to output ofM_(INV2); output of M_(INV3) being connected to input of M_(GATE); inputof M_(GATE) being connected to output of M_(INV3); and output ofM_(GATE) being connected to input of M_(INV2) and output of M_(INV1);the slave latch comprising: a first slave inverter, S_(INV1), a secondslave inverter, S_(INV2), a third slave inverter, S_(INV3), and a slavetransmission gate, S_(GATE); input of S_(INV1) being connected to outputof M_(INV2); input of S_(INV2) being connected to output of S_(INV1);output of S_(INV2) being connected to input of S_(INV3) and to a dataoutput Q; input of S_(INV3) being connected to output of S_(INV2);output of S_(INV3) being connected to input of S_(GATE); and output ofS_(GATE) being connected to input of S_(INV2) and output of S_(INV1);and the B&R circuit comprising: a first transistor, M₁, M₁ having anM₁-source, an M₁-gate, and an M₁-drain; a second transistor, M₂, M₂having an M₂-source, an M₂-gate, and an M₂-drain; a third transistor,M₃, M₃ having an M₃-source, an M₃-gate, and an M₃-drain; a fourthtransistor, M₄, M₄ having an M₄-source, an M₄-gate, and an M₄-drain; afirst branch comprising M₁, M₃, and ground, GND; a second branchcomprising M₂, M₄, and GND; each of M₁ and M₂ is a metal oxidesemiconductor field effect transistor (MOSFET); each of M₃ and M₄ is aFeFET; M₁-drain being connected to M₃-source; M₁-gate being connected toa restore signal input signal and M₂-gate; M₁-source being connected toGND; M₂-drain being connected to M₄-source; M₂-gate being connected toM₁-gate; M₃-drain configured to be connected to a slave latch via thefirst branch; M₃-drain being connected to M₄-gate, M₄-drain, M₃-gate,and to the second branch; M₃-gate being connected to M₄-gate, M₄-drain,M₃-drain, and to the second branch; M₃-source being connected toM₁-drain; M₄-drain configured to be connected to the slave latch via thesecond branch; M₄-drain being connected to M₃-gate, M₃-drain, M₄-gate,and to the first branch; M₄-gate being connected to M₃-gate, M₃-drain,M₄-drain, and to the first branch; and M₄-source being connected toM₂-drain.
 11. The NVM device recited in claim 9, wherein: M₃-drain beingconnected to output of S_(GATE), output of S_(INV1), and input ofS_(INV2), and M₄-drain being connected to input of S_(INV3), output ofS_(INV2), and data output Q.